| /Documentation/devicetree/bindings/mtd/ |
| D | st,stm32-fmc2-nand.yaml | 41 $ref: raw-nand-chip.yaml
64 - description: Chip select 0 data
65 - description: Chip select 0 command
66 - description: Chip select 0 address space
67 - description: Chip select 1 data
68 - description: Chip select 1 command
69 - description: Chip select 1 address space
89 - description: Chip select 0 data
90 - description: Chip select 0 command
91 - description: Chip select 0 address space
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| D | fsl-upm-nand.txt | 5 - reg : should specify localbus chip select and size used for the chip.
10 - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
11 The corresponding address lines are used to select the chip.
13 (R/B#). For multi-chip devices, "n" GPIO definitions are required
17 - fsl,upm-wait-flags : add chip-dependent short delays after running the
20 - chip-delay : chip dependent delay for transferring data from array to
24 Each flash chip described may optionally contain additional sub-nodes
55 /* Multi-chip NAND device */
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| D | nand-controller.yaml | 17 enforced even for simple controllers supporting only one chip.
33 Array of chip-select available to the controller. The first
34 entries are a 1:1 mapping of the available chip-select on the
36 chip-select as needed may follow and should be phandles of GPIO
37 lines. 'reg' entries of the NAND chip subnodes become indexes of
45 $ref: raw-nand-chip.yaml#
65 /* NAND chip specific properties */
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| /Documentation/translations/zh_CN/core-api/ |
| D | genericirq.rst | 107 这个高层IRQ处理函数只使用由分配的芯片描述符结构体引用的desc->irq_data.chip
178 desc->irq_data.chip->irq_unmask(data);
184 desc->irq_data.chip->irq_mask(data);
189 chip->irq_ack(data);
194 if (chip->irq_mask_ack) {
195 chip->irq_mask_ack(data);
197 chip->irq_mask(data);
198 chip->irq_ack(data);
218 desc->irq_data.chip->irq_mask_ack();
220 desc->irq_data.chip->irq_unmask();
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| /Documentation/userspace-api/gpio/ |
| D | chardev.rst | 28 The API is based around two major objects, the :ref:`gpio-v2-chip` and the
31 .. _gpio-v2-chip:
33 Chip chapter
36 The Chip represents a single GPIO chip and is exposed to userspace using device
39 Each chip supports a number of GPIO lines,
40 :c:type:`chip.lines<gpiochip_info>`. Lines on the chip are identified by an
41 ``offset`` in the range from 0 to ``chip.lines - 1``, i.e. `[0,chip.lines)`.
43 Lines are requested from the chip using gpio-v2-get-line-ioctl.rst
44 and the resulting line request is used to access the GPIO chip's lines or
53 The following operations may be performed on the chip:
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| D | chardev_v1.rst | 20 The API is based around three major objects, the :ref:`gpio-v1-chip`, the
26 .. _gpio-v1-chip:
28 Chip chapter
31 The Chip represents a single GPIO chip and is exposed to userspace using device
34 Each chip supports a number of GPIO lines,
35 :c:type:`chip.lines<gpiochip_info>`. Lines on the chip are identified by an
36 ``offset`` in the range from 0 to ``chip.lines - 1``, i.e. `[0,chip.lines)`.
38 Lines are requested from the chip using either gpio-get-linehandle-ioctl.rst
39 and the resulting line handle is used to access the GPIO chip's lines, or
49 The following operations may be performed on the chip:
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| /Documentation/userspace-api/media/v4l/ |
| D | vidioc-dbg-g-chip-info.rst | 41 applications must not use it. When you found a chip specific bug, please
53 the driver stores information about the selected chip in the ``name``
57 selects the nth bridge 'chip' on the TV card. You can enumerate all
60 zero always selects the bridge chip itself, e. g. the chip connected to
62 bridge chip such as an AC97 register block.
68 On success, the ``name`` field will contain a chip name and the
89 - See :ref:`name-chip-match-types` for a list of possible types.
94 - Match a chip by this number, interpreted according to the ``type``
98 - Match a chip by this name, interpreted according to the ``type``
115 - How to match the chip, see :ref:`name-v4l2-dbg-match`.
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| D | vidioc-dbg-g-register.rst | 55 ``match.type`` and ``match.addr`` or ``match.name`` fields select a chip
66 selects the nth non-sub-device chip on the TV card. The number zero
67 always selects the host chip, e. g. the chip connected to the PCI or USB
99 - See :ref:`chip-match-types` for a list of possible types.
104 - Match a chip by this number, interpreted according to the ``type``
108 - Match a chip by this name, interpreted according to the ``type``
122 - How to match the chip, see :c:type:`v4l2_dbg_match`.
138 .. flat-table:: Chip Match Types
145 - Match the nth chip on the card, zero for the bridge chip. Does not
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| /Documentation/core-api/ |
| D | genericirq.rst | 65 the 'chip details'.
69 and only need to add the chip-level specific code. The separation is
71 IRQ flow itself but not in the chip details - and thus provides a more
106 3. Chip-level hardware encapsulation
116 interrupt chip structure which are assigned to this interrupt.
120 high-level IRQ handling function only uses desc->irq_data.chip
121 primitives referenced by the assigned chip descriptor structure.
183 The helper functions call the chip primitives and are used by the
189 desc->irq_data.chip->irq_unmask(data);
195 desc->irq_data.chip->irq_mask(data);
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| /Documentation/devicetree/bindings/power/reset/ |
| D | ocelot-reset.txt | 11 - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
12 "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
16 compatible = "mscc,ocelot-chip-reset";
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| D | ltc2952-poweroff.txt | 3 This chip is used to externally trigger a system shut down. Once the trigger has
4 been sent, the chip's watchdog has to be reset to gracefully shut down.
11 chip's watchdog line
13 chip's kill line
17 chip's trigger line. If this property is not set, the
18 trigger function is ignored and the chip is kept alive
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| /Documentation/hwmon/ |
| D | w83773g.rst | 22 chip. This chip implements one local and two remote sensors.
23 The chip also features offsets for the two remote sensors which get added to
24 the input readings. The chip does all the scaling by itself and the driver
27 The chip is wired over I2C/SMBus and specified over a temperature
32 The chip supports only temperature measurement. The driver exports
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| D | pmbus-core.rst | 79 functionality which has been implemented by several chip vendors and is thus
97 Virtual commands have to be handled in device specific driver code. Chip driver
99 negative error code if not. The chip driver may return -ENODATA or any other
102 core code will abort if the chip driver returns an error code when reading
104 send a virtual command to a chip).
115 provided by chip manufacturers in device datasheets.
116 - Supported chip functionality can be provided to the core driver. This may be
128 by both the I2C adapter and by the PMBus chip, it is by default enabled.
131 communication with the PMBus chip.
136 Functions provided by chip driver
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| /Documentation/admin-guide/gpio/ |
| D | gpio-mockup.rst | 29 and the first number after the last of this chip. If the base GPIO
31 parameter is the number of lines exposed by the chip.
36 the second 16 and the third 4. The base GPIO for the third chip is set
44 The name format is: gpio-mockup-X-Y where X is mockup chip's ID
50 Each mockup chip creates its own subdirectory in /sys/kernel/debug/gpio-mockup/.
51 The directory is named after the chip's label. A symlink is also created, named
52 after the chip's name, which points to the label directory.
55 name of the attribute represents the line's offset in the chip.
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| /Documentation/devicetree/bindings/spi/ |
| D | sprd,spi-adi.yaml | 16 analog chip (such as PMIC) from digital chip. ADI controller follows the SPI
21 48 hardware channels to access analog chip. For 2 software read/write channels,
22 users should set ADI registers to access analog chip. For hardware channels,
24 which means we can just link one analog chip address to one hardware channel,
25 then users can access the mapped analog chip address by this hardware channel
31 the analog chip address where user want to access by hardware components.
33 Since we have multi-subsystems will use unique ADI to access analog chip, when
76 - description: The analog chip address where user want to access by
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| /Documentation/w1/slaves/ |
| D | w1_ds2438.rst | 18 The DS2438 chip provides several functions that are desirable to carry in
20 Because the ability of temperature, current and voltage measurement, the chip
41 This file provides full 8 bytes of the chip Page 0 (00h).
49 This file provides full 8 bytes of the chip Page 1 (01h).
57 This file controls the 2-byte Offset Register of the chip.
59 current measurement done by the chip. Changing this register to the two's complement
61 the chip, canceling offset errors in the current ADC.
67 command of the chip, afterwards the temperature is read from the device
76 command of the chip.
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| /Documentation/devicetree/bindings/input/touchscreen/ |
| D | melfas_mip4.txt | 5 - reg: I2C slave address of the chip (0x48 or 0x34)
6 - interrupts: interrupt to which the chip is connected
9 - ce-gpios: GPIO connected to the CE (chip enable) pin of the chip
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| /Documentation/scsi/ |
| D | 53c700.rst | 33 Using the Chip Core Driver
36 In order to plumb the 53c700 chip core driver into a working SCSI
37 driver, you need to know three things about the way the chip is wired
45 the SCSI Id from the card bios or whether the chip is wired for
54 asynchronous dividers for the chip. As a general rule of thumb,
56 consistent with the best operation of the chip (although some choose
58 of an extra clock chip). The best operation clock speeds are:
97 you have a card with more than one chip on it and you can read a
106 Set to the clock speed of the chip in MHz.
124 Set to 1 if the chip drives a differential bus.
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| /Documentation/misc-devices/ |
| D | bh1770glc.rst | 25 ALS produces 16 bit lux values. The chip contains interrupt logic to produce
28 Proximity part contains IR-led driver up to 3 IR leds. The chip measures
35 Proximity low interrupt doesn't exists in the chip. This is simulated
41 Chip state is controlled via runtime pm framework when enabled in config.
52 RO - shows detected chip type and version
55 RW - enable / disable chip
59 - 1 enables the chip
60 - 0 disables the chip
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| /Documentation/arch/powerpc/ |
| D | vcpudispatch_stats.rst | 10 on their associated physical processor chip. However, under certain
11 scenarios, vcpus may be dispatched on a different processor chip (away
34 as last time, but within the same chip
35 4. number of times this vcpu was dispatched on a different chip
42 6. number of times this vcpu was dispatched in its home node (chip)
70 the same chip, while 30 dispatches were on a different chip compared to
75 outside its home node, on a neighbouring chip.
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | arm,pl172.txt | 17 - ranges: Must contain one or more chip select memory regions.
28 Child chip-select (cs) nodes contain the memory devices nodes connected to
44 - mpmc,cs: Chip select number. Indicates to the pl0172 driver
47 - mpmc,memory-width: Width of the chip select memory. Must be equal to
54 - mpmc,cs-active-high: Set chip select polarity to active high.
67 - mpmc,write-enable-delay: Delay from chip select assertion to write
70 - mpmc,output-enable-delay: Delay from chip select assertion to output
73 - mpmc,write-access-delay: Delay from chip select assertion to write
76 - mpmc,read-access-delay: Delay from chip select assertion to read
88 Example for pl172 with nor flash on chip select 0 shown below.
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| /Documentation/devicetree/bindings/mips/cavium/ |
| D | bootbus.txt | 3 The Octeon Boot Bus is a configurable parallel bus with 8 chip
4 selects. Each chip select is independently configurable.
13 - #address-cells: Must be <2>. The first cell is the chip select
14 within the bootbus. The second cell is the offset from the chip select.
19 parent-bus-address, length) for each active chip select. If the
20 length element for any triplet is zero, the chip select is disabled,
23 The configuration parameters for each chip select are stored in child
29 - cavium,cs-index: A single cell indicating the chip select that
60 the bus for this chip select.
72 /* The chip select number and offset */
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| /Documentation/sound/kernel-api/ |
| D | writing-an-alsa-driver.rst | 167 This directory contains the codes for ASoC (ALSA System on Chip)
224 /* definition of the chip-specific record */
232 /* chip-specific destructor
235 static int snd_mychip_free(struct mychip *chip)
248 /* chip-specific constructor
255 struct mychip *chip;
268 /* allocate a chip-specific data with zero filled */
269 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
270 if (chip == NULL)
273 chip->card = card;
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| /Documentation/devicetree/bindings/arm/ |
| D | syna.txt | 48 * Marvell Berlin2 chip control binding
50 Marvell Berlin SoCs have a chip control register set providing several
53 chip control registers, so there should be a single DT node only providing the
61 BG2/BG2CD: chip control register set
62 BG2Q: chip control register set and cpu pll registers
77 chip: chip-control@ea0000 {
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| /Documentation/driver-api/ |
| D | mtdnand.rst | 58 via pointers in the NAND chip description structure. The board driver
62 function which is suitable for the detected chip type.
74 modified. Most of these values are calculated from the chip geometry
84 suitable for the detected chip type.
102 chip description structure.
108 the ioremap'ed chip address. You can allocate the nand_chip structure
109 using kmalloc or you can allocate it statically. The NAND chip structure
153 NAND chip(s). The access can be done by GPIO pins or by address lines.
175 by a chip select decoder.
194 If the hardware interface has the ready busy pin of the NAND chip
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