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/Documentation/devicetree/bindings/access-controllers/
Daccess-controllers.yaml4 $id: http://devicetree.org/schemas/access-controllers/access-controllers.yaml#
7 title: Generic Domain Access Controllers
13 Common access controllers properties
15 Access controllers are in charge of stating which of the hardware blocks under
22 controller provided by access-controllers property. In this case, the device
31 Access controllers are typically used to set/read the permissions of a
36 Each node can be a consumer for the several access controllers.
44 Number of cells in an access-controllers specifier;
51 A list of access-controllers names, sorted in the same order as
52 access-controllers entries. Consumer drivers will use
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/Documentation/devicetree/bindings/mmc/
Dsdhci-omap.txt8 - compatible: Should be "ti,omap2430-sdhci" for omap2430 controllers
9 Should be "ti,omap3-sdhci" for omap3 controllers
10 Should be "ti,omap4-sdhci" for omap4 and ti81 controllers
11 Should be "ti,omap5-sdhci" for omap5 controllers
12 Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
14 Should be "ti,am335-sdhci" for am335x controllers
15 Should be "ti,am437-sdhci" for am437x controllers
Dk3-dw-mshc.txt15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
Dti-omap-hsmmc.txt12 Should be "ti,omap2-hsmmc", for OMAP2 controllers
13 Should be "ti,omap3-hsmmc", for OMAP3 controllers
14 Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
15 Should be "ti,omap4-hsmmc", for OMAP4 controllers
16 Should be "ti,am33xx-hsmmc", for AM335x controllers
17 Should be "ti,k2g-hsmmc", "ti,omap4-hsmmc" for 66AK2G controllers.
Dsdhci.txt1 The properties specific for SD host controllers. For properties shared by MMC
2 host controllers refer to the mmc[1] bindings.
/Documentation/input/devices/
Dxpad.rst2 xpad - Linux USB driver for Xbox compatible controllers
6 controllers. It has a long history and has enjoyed considerable usage
11 This only affects Original Xbox controllers. All later controller models
14 Rumble is supported on some models of Xbox 360 controllers but not of
15 Original Xbox controllers nor on Xbox One controllers. As of writing
39 unknown controllers.
42 Normal Controllers
77 of buttons, see section 0.3 - Unknown Controllers
82 Unknown Controllers
95 All generations of Xbox controllers speak USB over the wire.
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/Documentation/devicetree/bindings/i2c/
Dnvidia,tegra20-i2c.yaml39 Tegra114 has 5 generic I2C controllers. This controller is very much
52 Tegra124 has 6 generic I2C controllers. These controllers are very
57 Tegra210 has 6 generic I2C controllers. These controllers are very
66 the regular I2C controllers with a few exceptions. The I2C registers
72 Tegra186 has 9 generic I2C controllers, two of which are in the AON
73 (always-on) partition of the SoC. All of these controllers are very
77 Tegra194 has 8 generic I2C controllers, two of which are in the AON
78 (always-on) partition of the SoC. All of these controllers are very
79 similar to those found on Tegra186. However, these controllers have
101 Module reset. This property is optional for controllers in Tegra194,
/Documentation/devicetree/bindings/phy/
Drealtek,usb3phy.yaml16 support multiple XHCI controllers. One PHY device node maps to one XHCI
20 The USB architecture includes three XHCI controllers.
22 controllers.
30 The USB architecture includes three XHCI controllers.
31 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
38 The USB architecture includes three XHCI controllers.
39 Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
Drealtek,usb2phy.yaml16 support multiple XHCI controllers. One PHY device node maps to one XHCI
20 The USB architecture includes three XHCI controllers.
22 controllers.
30 The USB architecture includes two XHCI controllers.
38 The USB architecture includes three XHCI controllers.
39 Each XHCI maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#2.
46 The USB architecture includes three XHCI controllers.
47 Each xhci maps to one USB 2.0 PHY and map one USB 3.0 PHY on controllers#0.
54 The USB architecture includes three XHCI controllers.
/Documentation/ABI/testing/
Dsysfs-bus-pci-drivers-ehci_hcd7 PCI-based EHCI USB controllers (i.e., high-speed USB-2.0
8 controllers) are often implemented along with a set of
9 "companion" full/low-speed USB-1.1 controllers. When a
35 Note: Some EHCI controllers do not have companions; they
38 mechanism will not work with such controllers. Also, it
/Documentation/devicetree/bindings/memory-controllers/
Drenesas,dbsc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#
7 title: Renesas DDR Bus Controllers
13 Renesas SoCs contain one or more memory controllers. These memory
14 controllers differ from one SoC variant to another, and are called by
/Documentation/devicetree/bindings/usb/
Dusb-drd.yaml25 Tells Dual-Role USB controllers that we want to work on a particular
26 mode. In case this attribute isn't passed via DT, USB DRD controllers
34 Tells OTG controllers we want to disable OTG HNP. Normally HNP is the
41 Tells OTG controllers we want to disable OTG SRP. SRP is optional for OTG
47 Tells OTG controllers we want to disable OTG ADP. ADP is optional for OTG
Dusb.yaml37 Tells USB controllers that we want to configure the core to support a
41 selected. In case this isn't passed via DT, USB controllers should
48 Tells USB controllers we want to work up to a certain speed. In case this
49 isn't passed via DT, USB controllers should default to their maximum HW
Dpxa-usb.txt1 PXA USB controllers
6 - compatible: Should be "marvell,pxa-ohci" for USB controllers
35 - compatible: Should be "marvell,pxa270-udc" for USB controllers
/Documentation/PCI/endpoint/
Dpci-endpoint-cfs.rst25 The pci_ep configfs has two directories at its root: controllers and
27 the *controllers* directory and every EPF driver present in the system
32 .. controllers/
38 Every registered EPF driver will be listed in controllers directory. The
94 Every registered EPC device will be listed in controllers directory. The
98 /sys/kernel/config/pci_ep/controllers/
119 | controllers/
Dpci-ntb-howto.rst31 # ls /sys/kernel/config/pci_ep/controllers
111 NTB function device should be attached to two PCI endpoint controllers
117 # ln -s controllers/2900000.pcie-ep/ functions/pci-epf-ntb/func1/primary
118 # ln -s controllers/2910000.pcie-ep/ functions/pci-epf-ntb/func1/secondary
120 Once the above step is completed, both the PCI endpoint controllers are ready to
128 field should be populated with '1'. For NTB, both the PCI endpoint controllers
131 # echo 1 > controllers/2900000.pcie-ep/start
132 # echo 1 > controllers/2910000.pcie-ep/start
/Documentation/devicetree/bindings/gpio/
Dgpio-ath79.txt8 - reg: Base address and size of the controllers memory area
15 - interrupts: Interrupt specifier for the controllers interrupt.
21 Interrupt Controllers bindings used by client devices.
/Documentation/devicetree/bindings/interrupt-controller/
Dqca,ath79-misc-intc.txt9 - reg: Base address and size of the controllers memory area
10 - interrupts: Interrupt specifier for the controllers interrupt.
19 Interrupt Controllers bindings used by client devices.
Dmsi.txt1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
22 MSI controllers may have restrictions on permitted payloads.
31 MSI controllers:
68 MSI controllers listed in the msi-parent property.
131 * Can generate MSIs to all of the MSI controllers.
/Documentation/devicetree/bindings/watchdog/
Daspeed,ast2400-wdt.yaml7 title: Aspeed watchdog timer controllers
43 Specifying 'soc' will reset a configurable subset of the SoC's controllers
44 on a timeout event. Controllers critical to the SoC's operation may remain
45 untouched. The set of SoC controllers to reset may be specified via the
49 Specifying 'system' will reset all controllers on a timeout event, as if
/Documentation/devicetree/bindings/memory-controllers/ddr/
Djedec,lpddr-channel.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
71 $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
80 $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
89 $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
98 $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml#
/Documentation/devicetree/bindings/clock/
Dmarvell,pxa1928.txt1 * Marvell PXA1928 Clock Controllers
4 controllers within the PXA1928 SoC. The PXA1928 contains 3 clock controller
/Documentation/devicetree/bindings/input/
Dtps65218-pwrbutton.txt13 - <2>: For controllers compatible with tps65217
14 - <3 IRQ_TYPE_EDGE_BOTH>: For controllers compatible with tps65218
/Documentation/userspace-api/media/rc/
Drc-intro.rst10 remote controllers. Each manufacturer has their own type of control. It
18 However, remove controllers are more flexible than a normal input
/Documentation/devicetree/bindings/net/can/
Dgrcan.txt1 Aeroflex Gaisler GRCAN and GRHCAN CAN controllers.
3 The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core

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