Home
last modified time | relevance | path

Searched +full:cortex +full:- +full:m4 (Results 1 – 11 of 11) sorted by relevance

/Documentation/devicetree/bindings/remoteproc/
Dst,stm32-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/st,stm32-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Fabien Dessenne <fabien.dessenne@foss.st.com>
15 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
19 const: st,stm32mp1-m4
31 reset-names:
33 - const: mcu_rst
34 - const: hold_boot
[all …]
Dfsl,imx-rproc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/fsl,imx-rproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Co-Processor
10 This binding provides support for ARM Cortex M4 Co-processor found on some NXP iMX SoCs.
13 - Peng Fan <peng.fan@nxp.com>
18 - fsl,imx6sx-cm4
19 - fsl,imx7d-cm4
20 - fsl,imx7ulp-cm4
[all …]
Dmtk,scp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tinghan Shen <tinghan.shen@mediatek.com>
13 This binding provides support for ARM Cortex M4 Co-processor found on some
19 - mediatek,mt8183-scp
20 - mediatek,mt8186-scp
21 - mediatek,mt8188-scp
22 - mediatek,mt8188-scp-dual
23 - mediatek,mt8192-scp
[all …]
Dti,omap-remoteproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ti,omap-remoteproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Suman Anna <s-anna@ti.com>
13 The OMAP family of SoCs usually have one or more slave processor sub-systems
14 that are used to offload some of the processor-intensive tasks, or to manage
17 The processor cores in the sub-system are usually behind an IOMMU, and may
18 contain additional sub-modules like Internal RAM and/or ROMs, L1 and/or L2
21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
[all …]
/Documentation/arch/arm/stm32/
Dstm32f429-overview.rst6 ------------
8 The STM32F429 is a Cortex-M4 MCU aimed at various applications.
11 - ARM Cortex-M4 up to 180MHz with FPU
12 - 2MB internal Flash Memory
13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
14 - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
15 - LCD controller & Camera interface
16 - Cryptographic processor
19 ---------
23 …www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
8 which comes with a Cortex-A5/Cortex-M4 combination).
11 - compatible: "fsl,vf610-mscm-ir"
12 - reg: the register range of the MSCM Interrupt Router
13 - fsl,cpucfg: The handle to the MSCM CPU configuration node, required
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
23 mscm_ir: interrupt-controller@40001800 {
24 compatible = "fsl,vf610-mscm-ir";
27 interrupt-controller;
[all …]
/Documentation/devicetree/bindings/arm/stm32/
Dst,mlahb.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 ML-AHB interconnect
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
11 - Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
14 These bindings describe the STM32 SoCs ML-AHB interconnect bus which connects
15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
23 - $ref: /schemas/simple-bus.yaml#
[all …]
/Documentation/devicetree/bindings/arm/
Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
59 On 32-bit ARM v7 or later systems this property is
68 On ARM v8 64-bit systems this property is required
71 * If cpus node's #address-cells property is set to 2
79 * If cpus node's #address-cells property is set to 1
[all …]
Dfsl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
17 - description: i.MX1 based Boards
19 - enum:
20 - armadeus,imx1-apf9328
21 - fsl,imx1ads
22 - const: fsl,imx1
24 - description: i.MX23 based Boards
[all …]
/Documentation/devicetree/bindings/firmware/
Dfsl,scu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 The System Controller Firmware (SCFW) is a low-level system function
14 which runs on a dedicated Cortex-M core to provide power, clock, and
17 The AP communicates with the SC using a multi-ported MU module found
26 const: fsl,imx-scu
28 clock-controller:
31 $ref: /schemas/clock/fsl,scu-clk.yaml
[all …]
/Documentation/devicetree/bindings/mfd/
Dgoogle,cros-ec.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Benson Leung <bleung@chromium.org>
11 - Guenter Roeck <groeck@chromium.org>
22 - description:
24 const: google,cros-ec-i2c
25 - description:
27 const: google,cros-ec-spi
[all …]