Searched full:cortex (Results 1 – 25 of 98) sorted by relevance
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| /Documentation/devicetree/bindings/arm/ |
| D | pmu.yaml | 31 - arm,cortex-a5-pmu
32 - arm,cortex-a7-pmu
33 - arm,cortex-a8-pmu
34 - arm,cortex-a9-pmu
35 - arm,cortex-a12-pmu
36 - arm,cortex-a15-pmu
37 - arm,cortex-a17-pmu
38 - arm,cortex-a32-pmu
39 - arm,cortex-a34-pmu
40 - arm,cortex-a35-pmu
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| D | cpus.yaml | 123 - arm,cortex-a5
124 - arm,cortex-a7
125 - arm,cortex-a8
126 - arm,cortex-a9
127 - arm,cortex-a12
128 - arm,cortex-a15
129 - arm,cortex-a17
130 - arm,cortex-a32
131 - arm,cortex-a34
132 - arm,cortex-a35
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| D | arm,scu.yaml | 13 As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
18 - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
20 - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
28 - arm,cortex-a9-scu
29 - arm,cortex-a5-scu
44 compatible = "arm,cortex-a9-scu";
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| D | arm,corstone1000.yaml | 15 provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
18 Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
33 - description: Corstone1000 MPS3 it has 1 Cortex-A35 CPU core in a FPGA
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| D | arm,realview.yaml | 14 Cortex-A8, and Cortex-A9 CPUs. This included new features compared to the
38 - description: ARM RealView Platform Baseboard for Cortex-A8 (HBI-0178,
40 Cortex CPU family, including a Cortex-A8 test chip.
43 - description: ARM RealView Platform Baseboard Explore for Cortex-A9
44 (HBI-0182 and HBI-0183) was the reference platform for the Cortex-A9
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| D | arm,vexpress-juno.yaml | 15 multicore Cortex-A class systems. The Versatile Express family contains both
45 - description: CoreTile Express A9x4 (V2P-CA9) has 4 Cortex A9 CPU cores
51 - description: CoreTile Express A5x2 (V2P-CA5s) has 2 Cortex A5 CPU cores
53 and Jazelle support in the Cortex A5 family. See ARM DUI 0541C.
57 - description: Coretile Express A15x2 (V2P-CA15) has 2 Cortex A15 CPU
63 - description: CoreTile Express A15x4 (V2P-CA15, HBI-0237A) has 4 Cortex
70 - description: Coretile Express A15x2 A7x3 (V2P-CA15_A7) has 2 Cortex A15
71 CPU cores and 3 Cortex A7 cores in a big.LITTLE MPCore configuration
76 - description: LogicTile Express 20MG (V2F-1XV7) has 2 Cortex A53 CPU
84 AArch64 CPU cores. It has 2 Cortex A57 CPU cores and 4 Cortex A53
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | silicon-errata.txt | 63 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
64 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
65 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
66 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
67 | ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
68 | ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
69 | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
70 | ARM | Cortex-A57 | #852523 | N/A |
71 | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | silicon-errata.txt | 67 | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
68 | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
69 | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 |
70 | ARM | Cortex-A53 | #819472 | ARM64_ERRATUM_819472 |
71 | ARM | Cortex-A53 | #845719 | ARM64_ERRATUM_845719 |
72 | ARM | Cortex-A53 | #843419 | ARM64_ERRATUM_843419 |
73 | ARM | Cortex-A57 | #832075 | ARM64_ERRATUM_832075 |
74 | ARM | Cortex-A57 | #852523 | N/A |
75 | ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,global_timer.yaml | 13 Cortex-A9 are often associated with a per-core Global timer.
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
43 compatible = "arm,cortex-a9-global-timer";
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| D | arm,twd-timer.yaml | 13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
23 - arm,cortex-a9-twd-timer
24 - arm,cortex-a5-twd-timer
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| /Documentation/devicetree/bindings/watchdog/ |
| D | arm,twd-wdt.yaml | 13 ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
23 - arm,cortex-a9-twd-wdt
24 - arm,cortex-a5-twd-wdt
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| /Documentation/devicetree/bindings/cpu/ |
| D | cpu-topology.txt | 278 compatible = "arm,cortex-a57";
286 compatible = "arm,cortex-a57";
294 compatible = "arm,cortex-a57";
302 compatible = "arm,cortex-a57";
310 compatible = "arm,cortex-a57";
318 compatible = "arm,cortex-a57";
326 compatible = "arm,cortex-a57";
334 compatible = "arm,cortex-a57";
342 compatible = "arm,cortex-a57";
350 compatible = "arm,cortex-a57";
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| /Documentation/devicetree/bindings/arm/cpu-enable-method/ |
| D | al,alpine-smp | 12 Compatible CPUs: "arm,cortex-a15"
38 compatible = "arm,cortex-a15";
44 compatible = "arm,cortex-a15";
50 compatible = "arm,cortex-a15";
56 compatible = "arm,cortex-a15";
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| D | nuvoton,npcm750-smp | 10 Compatible CPUs: "arm,cortex-a9"
14 This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and
26 compatible = "arm,cortex-a9";
35 compatible = "arm,cortex-a9";
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,gic.yaml | 30 - arm,cortex-a15-gic
31 - arm,cortex-a7-gic
32 - arm,cortex-a5-gic
33 - arm,cortex-a9-gic
44 - arm,cortex-a15-gic
45 - arm,cortex-a7-gic
53 - const: arm,cortex-a15-gic
132 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
133 - items: # for "arm,cortex-a9-gic"
193 compatible = "arm,cortex-a9-gic";
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-dt.txt | 31 compatible = "arm,cortex-a9";
45 compatible = "arm,cortex-a9";
51 compatible = "arm,cortex-a9";
57 compatible = "arm,cortex-a9";
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| D | cpufreq-mediatek.txt | 68 compatible = "arm,cortex-a7";
78 compatible = "arm,cortex-a7";
84 compatible = "arm,cortex-a7";
90 compatible = "arm,cortex-a7";
188 compatible = "arm,cortex-a53";
200 compatible = "arm,cortex-a53";
212 compatible = "arm,cortex-a72";
224 compatible = "arm,cortex-a72";
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| /Documentation/arch/arm/ |
| D | sunxi.rst | 20 * ARM Cortex-A8 based SoCs
47 * Single ARM Cortex-A7 based SoCs
54 * Dual ARM Cortex-A7 based SoCs
71 * Quad ARM Cortex-A7 based SoCs
123 * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
130 * Octa ARM Cortex-A7 based SoCs
141 * Quad ARM Cortex-A53 based SoCs
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| /Documentation/arch/arm/stm32/ |
| D | stm32mp13-overview.rst | 8 The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications.
11 - One Cortex-A7 application core
18 - Cortex-A7 core running up to @900MHz
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| D | stm32mp151-overview.rst | 8 The STM32MP151 is a Cortex-A MPU aimed at various applications.
11 - Single Cortex-A7 application core
18 - Cortex-A7 core running up to @800MHz
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| D | stm32f746-overview.rst | 8 The STM32F746 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
30 …/www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-serie…
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| D | stm32f769-overview.rst | 8 The STM32F769 is a Cortex-M7 MCU aimed at various applications.
11 - Cortex-M7 core running up to @216MHz
32 …/www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32-high-pe…
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| /Documentation/devicetree/bindings/arm/stm32/ |
| D | st,mlahb.yaml | 15 a Cortex-M subsystem with dedicated memories. The MCU SRAM and RETRAM memory
17 using different buses (see [2]): balancing the Cortex-M firmware accesses
34 remote Cortex-M processor. Each memory region, is declared with
36 - param 1: device base address (Cortex-M processor address)
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| /Documentation/arch/arm64/ |
| D | silicon-errata.rst | 61 | ARM | Cortex-A510 | #2457168 | ARM64_ERRATUM_2457168 |
63 | ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
65 | ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
67 | ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 |
69 | ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
71 | ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
73 | ARM | Cortex-A510 | #2441009 | ARM64_ERRATUM_2441009 |
75 | ARM | Cortex-A510 | #2658417 | ARM64_ERRATUM_2658417 |
77 | ARM | Cortex-A510 | #3117295 | ARM64_ERRATUM_3117295 |
79 | ARM | Cortex-A520 | #2966298 | ARM64_ERRATUM_2966298 |
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| /Documentation/devicetree/bindings/opp/ |
| D | opp-v2.yaml | 24 * Example 1: Single cluster Dual-core ARM cortex A9, switch DVFS states
32 compatible = "arm,cortex-a9";
43 compatible = "arm,cortex-a9";
173 compatible = "arm,cortex-a7";
184 compatible = "arm,cortex-a7";
195 compatible = "arm,cortex-a15";
206 compatible = "arm,cortex-a15";
339 compatible = "arm,cortex-a7";
393 compatible = "arm,cortex-a7";
424 * Example 7: Single cluster Quad-core ARM cortex A53, OPP points from firmware,
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