Searched full:cycle (Results 1 – 25 of 243) sorted by relevance
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| /Documentation/devicetree/bindings/input/ |
| D | pwm-vibrator.yaml | 14 strength increases based on the duty cycle of the enable PWM channel
15 (100% duty cycle meaning strongest vibration, 0% meaning no vibration).
18 driven at fixed duty cycle. If available this is can be used to increase
39 direction-duty-cycle-ns:
41 Duty cycle of the direction PWM channel in nanoseconds,
58 direction-duty-cycle-ns = <1000000000>;
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| D | azoteq,iqs7222.yaml | 324 "^cycle-[0-9]$":
326 description: Represents a conversion cycle serving two sensing channels.
333 description: Specifies the cycle's conversion period.
339 description: Specifies the cycle's conversion frequency fraction.
348 description: Specifies the CTx pin(s) associated with the cycle.
372 Specifies the cycle's sensing mode as follows:
390 description: Specifies the cycle's current reference level.
396 description: Specifies the cycle's current reference trim.
845 "^cycle-[0-9]$":
946 cycle-0 {
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| /Documentation/devicetree/bindings/regulator/ |
| D | pwm-regulator.yaml | 19 duty-cycle values must be provided via DT. Limitations are that the
21 Intermediary duty-cycle values which would normally allow finer grained
29 appropriate duty-cycle values. This allows for a much more fine grained
31 make an assumption that a %50 duty-cycle value will cause the regulator
49 description: Voltage and Duty-Cycle table.
54 - description: duty-cycle in percent (%)
63 Integer value encoding the duty cycle unit. If not
75 Duty cycle values are expressed in pwm-dutycycle-unit.
104 * Inverted PWM logic, and the duty cycle range is limited
119 /* Voltage Duty-Cycle */
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| /Documentation/admin-guide/perf/ |
| D | alibaba_pmu.rst | 26 - Group 0: PMU Cycle Counter. This group has one pair of counters
27 pmu_cycle_cnt_low and pmu_cycle_cnt_high, that is used as the cycle count
61 -e ali_drw_21000/cycle/ \
65 -e ali_drw_21080/cycle/ \
69 -e ali_drw_23000/cycle/ \
73 -e ali_drw_23080/cycle/ \
77 -e ali_drw_25000/cycle/ \
81 -e ali_drw_25080/cycle/ \
85 -e ali_drw_27000/cycle/ \
89 -e ali_drw_27080/cycle/ -- sleep 10
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| /Documentation/hwmon/ |
| D | dme1737.rst | 167 cycle) of the input. The chip adjusts the sampling rate based on this value.
178 manual mode, the fan speed is set by writing the duty-cycle value to the
180 current duty-cycle as set by the fan controller in the chip. All PWM outputs
198 pwm[1-3]_auto_point2_pwm full-speed duty-cycle (255, i.e., 100%)
199 pwm[1-3]_auto_point1_pwm low-speed duty-cycle
200 pwm[1-3]_auto_pwm_min min-speed duty-cycle
208 The chip adjusts the output duty-cycle linearly in the range of auto_point1_pwm
211 auto_point1_temp_hyst value, the output duty-cycle is set to the auto_pwm_min
214 duty-cycle. If any of the temperatures rise above the auto_point3_temp value,
215 all PWM outputs are set to 100% duty-cycle.
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| D | vt1211.rst | 194 PWM Auto Point PWM Output Duty-Cycle
196 pwm[1-2]_auto_point4_pwm full speed duty-cycle (hard-wired to 255)
197 pwm[1-2]_auto_point3_pwm high speed duty-cycle
198 pwm[1-2]_auto_point2_pwm low speed duty-cycle
199 pwm[1-2]_auto_point1_pwm off duty-cycle (hard-wired to 0)
212 PWM output duty-cycle based on the input temperature:
215 Thermal Threshold Output Duty-Cycle Output Duty-Cycle
218 - full speed duty-cycle full speed duty-cycle
220 - high speed duty-cycle full speed duty-cycle
222 - low speed duty-cycle high speed duty-cycle
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| D | lm93.rst | 109 a minimum pulse width of 5 clocks (at 22.5kHz => 6.25% duty cycle), and
110 a maximum pulse width of 80 clocks (at 22.5kHz => 99.88% duty cycle).
115 contains a value controlling the duty cycle for the PWM signal used when
117 indicating minimum duty cycle and 15 indicating maximum.
148 and pwm2 are used to set the manual duty cycle; each is an integer (0-255)
149 where 0 is 0% duty cycle, and 255 is 100%. Note that the duty cycle values
153 cycle chosen by the h/w.
235 PWM Spin-Up Cycle
238 A spin-up cycle occurs when a PWM output is commanded from 0% duty cycle to
239 some value > 0%. The LM93 supports a minimum duty cycle during spin-up. These
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| D | max31790.rst | 42 pwm[1-6]_enable RW regulator mode, 0=disabled (duty cycle=0%), 1=manual mode, 2=rpm mode
43 pwm[1-6] RW read: current pwm duty cycle,
44 write: target pwm duty cycle (0-255)
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| D | f71882fg.rst | 153 There are 2 modes to specify the speed of the fan, PWM duty cycle (or DC
154 voltage) mode, where 0-100% duty cycle (0-100% of 12V) is specified. And RPM
176 You ask for a specific PWM duty cycle / DC voltage or a specific % of
187 * 3: Thermostat mode (Only available on the F8000 when in duty cycle mode)
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| /Documentation/devicetree/bindings/spi/ |
| D | renesas,sh-msiof.yaml | 119 - 50 # 0.5-clock-cycle delay
120 - 100 # 1-clock-cycle delay
121 - 150 # 1.5-clock-cycle delay
122 - 200 # 2-clock-cycle delay
129 - 50 # 0.5-clock-cycle delay
130 - 100 # 1-clock-cycle delay
131 - 150 # 1.5-clock-cycle delay
132 - 200 # 2-clock-cycle delay
133 - 300 # 3-clock-cycle delay
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| /Documentation/driver-api/thermal/ |
| D | cpu-idle-cooling.rst | 37 decrease. Acting on the idle state duration or the idle cycle
47 At a specific OPP, we can assume that injecting idle cycle on all CPUs
61 idle state for a specified time each control cycle, it provides
71 or decreased by modulating the duty cycle of the idle injection.
86 duty cycle 25%
90 the duty cycle percentage. When no mitigation is happening the cooling
91 device state is zero, meaning the duty cycle is 0%.
95 cycle (aka the cooling device state), the running duration can be
98 The governor will change the cooling device state thus the duty cycle
114 duty cycle 33%
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | mvebu-devbus.txt | 40 cycle from a slow device.
53 ALE[0] to the cycle that the first read data is sampled
57 - devbus,acc-next-ps: Defines the time delay between the cycle that
58 samples data N and the cycle that samples data N+1
64 DEV_OEn and DEV_CSn are asserted at the same cycle.
73 DEV_OEn and DEV_CSn are de-asserted at the same cycle
74 (the cycle of the last data sample).
76 DEV_OEn is always de-asserted the next cycle after
85 - devbus,ale-wr-ps: Defines the time delay from the ALE[0] negation cycle
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| D | ti,gpmc-child.yaml | 92 # Access time and cycle time timings (in nanoseconds) corresponding to
99 description: Start-cycle to first data valid delay
102 gpmc,rd-cycle-ns:
103 description: Total read cycle time
106 gpmc,wr-cycle-ns:
107 description: Total write cycle time
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| D | atmel,ebi.txt | 91 - atmel,smc-nwe-cycle-ns
92 - atmel,smc-nrd-cycle-ns
132 atmel,smc-nrd-cycle-ns = <107>;
133 atmel,smc-nwe-cycle-ns = <84>;
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| /Documentation/userspace-api/media/rc/ |
| D | lirc-set-send-duty-cycle.rst | 13 LIRC_SET_SEND_DUTY_CYCLE - Set the duty cycle of the carrier signal for
31 the total cycle. Values 0 and 100 are reserved.
36 Get/set the duty cycle of the carrier signal for IR transmit.
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| /Documentation/userspace-api/ |
| D | dcdbas.rst | 10 management interrupts and host control actions (system power cycle or
55 to perform a power cycle or power off of the system after the OS has finished
60 to schedule the driver to perform a power cycle or power off host control
67 Dell OpenManage performs the following steps to execute a power cycle or
82 perform a power cycle or power off host control action:
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-silicom | 14 This file allow user to power cycle the platform.
17 device. It returns to default value after power cycle.
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| D | sysfs-bus-iio-chemical-sunrise-co2 | 6 Writing '1' triggers a 'Factory' calibration cycle.
13 Writing '1' triggers a 'Background' calibration cycle.
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| D | sysfs-fs-xfs | 7 log. The LSN is exported in "cycle:basic block" format.
16 log. The LSN is exported in "cycle:basic block" format.
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| /Documentation/devicetree/bindings/mtd/ |
| D | fsmc-nand.txt | 25 one cycle, 255 means 256 cycles.
27 NAND flash in response to SMWAITn. Zero means 1 cycle,
30 command is asserted. Zero means one cycle, 255 means 256
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| /Documentation/devicetree/bindings/leds/irled/ |
| D | ir-spi-led.yaml | 26 duty-cycle:
55 duty-cycle = /bits/ 8 <60>;
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| /Documentation/devicetree/bindings/w1/ |
| D | w1-uart.yaml | 40 The baud rate for the 1-Wire write-0 cycle.
45 The baud rate for the 1-Wire write-1 and read cycle.
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| /Documentation/devicetree/bindings/bus/ |
| D | nvidia,tegra20-gmi.txt | 45 - nvidia,snor-rdy-active-before-data: Assert RDY signal one cycle before data.
54 Programming 0 means 1 clock cycle: actual cycle = programmed cycle + 1
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| /Documentation/devicetree/bindings/sound/ |
| D | qcom,q6dsp-lpass-ports.yaml | 90 0 = 0 bit clock cycle
91 1 = 1 bit clock cycle
92 2 = 2 bit clock cycle
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| /Documentation/devicetree/bindings/hwmon/ |
| D | adt7475.yaml | 45 the pwm uses a logic low output for 100% duty cycle. If set to 1 the pwm
46 uses a logic high output for 100% duty cycle.
71 - 3: The default PWM duty cycle in nanoseconds
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