| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 71 SR_IDLE * 1024 DFI clock cycles (DFI clocks freq is half of DRAM clock).
100 self-refresh mode. The controller, pi, PHY and DRAM clock will be gated
130 When the DRAM type is DDR3, this parameter defines the ODT disable
132 the ODT on the DRAM side and controller side are both disabled.
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, this parameter defines the PHY side DQ line
170 When the DRAM type is DDR3, this parameter defines the PHY side ODT
178 When the DRAM type is LPDDR3, this parameter defines then ODT disable
[all …]
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| D | samsung,exynos5422-dmc.yaml | 17 DRAM memory chips are connected. The driver is to monitor the controller in
55 phandle of the connected DRAM memory device. For more information please
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| D | calxeda-ddr-ctrlr.yaml | 12 purposes and to learn about the DRAM topology.
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| /Documentation/devicetree/bindings/arm/sunxi/ |
| D | allwinner,sun4i-a10-mbus.yaml | 51 - description: DRAM controller/PHY registers
57 - const: dram
63 - description: DRAM controller/PHY module clock
64 - description: Register bus clock, shared by MBUS and DRAM
70 - const: dram
141 dram-controller@1c01000 {
152 dram-controller@1c62000 {
156 reg-names = "mbus", "dram";
160 clock-names = "mbus", "dram", "bus";
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-39x-pinctrl.txt | 32 mpp14 14 gpio, dram(vttctrl), dev(we1), ua1(txd)
34 mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda)
52 mpp33 33 gpio, dram(deccerr), dev(ad3)
62 mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), nand(rb1)
69 mpp48 48 gpio, sata0(prsnt) [1], dram(vttctrl), tdm(pclk) [2], audio(mclk) [2], sd0(d4), pcie0(clkr…
73 mpp51 51 gpio, tdm(dtx) [2], audio(sdo) [2], dram(deccerr), ua2(txd)
78 mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
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| D | marvell,armada-38x-pinctrl.txt | 32 mpp14 14 gpio, ge0(rxd2), ptp(clk), dram(vttctrl), spi0(cs3), dev(we1), pcie3(clkreq)
34 mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), …
51 mpp33 33 gpio, dram(deccerr), dev(ad3)
61 mpp43 43 gpio, pcie0(clkreq), dram(vttctrl), dram(deccerr), spi1(cs2), dev(clkout), n…
66 mpp48 48 gpio, sata0(prsnt), dram(vttctrl), tdm(pclk), audio(mclk), sd0(d4), pcie0(cl…
69 mpp51 51 gpio, tdm(dtx), audio(sdo), dram(deccerr), ptp(trig)
74 mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
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| D | marvell,armada-xp-pinctrl.txt | 42 mpp21 21 gpio, ge0(rxd5), ge1(rxd3), lcd(d21), dram(bat)
54 mpp33 33 gpio, tdm(int4), sd0(d1), dram(bat), dram(vttctrl)
55 mpp34 34 gpio, tdm(int5), sd0(d2), sata0(prsnt), dram(deccerr)
69 dram(bat), spi1(cs4)
71 spi1(cs5), dram(vttctrl)
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| D | cortina,gemini-pinctrl.txt | 36 dram_default_pins: pinctrl-dram {
38 function = "dram";
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| D | marvell,armada-375-pinctrl.txt | 26 mpp10 10 gpio, dram(vttctrl), led(c1), nand(re)
59 mpp43 43 gpio, sata0(prsnt), dram(vttctrl)
80 mpp64 64 gpio, dram(vttctrl), led(p3)
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| /Documentation/devicetree/bindings/interconnect/ |
| D | mediatek,mt8183-emi.yaml | 22 | |->| DRAM | ---- | ----
23 |DRAM |->|scheduler|----- |GPU | |--- |DISP|
29 | change DRAM freq |--- |VENC|
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| /Documentation/hid/ |
| D | amd-sfh-hid.rst | 60 on that allocates the DRAM address for each and every sensor and passes it to MP2-PCIe driver. On
72 2. Data transfer via DRAM.
77 the PCI layer. MP2 firmware writes the command output to the access DRAM memory which the client
78 layer has allocated. Firmware always writes minimum of 32 bytes into DRAM. So as a protocol driver
79 shall allocate minimum of 32 bytes DRAM space.
103 | | | Allocate the DRAM | Enable |
136 | | | Read the DRAM data for| | |
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| /Documentation/devicetree/bindings/clock/ |
| D | allwinner,sun4i-a10-pll5-clk.yaml | 7 title: Allwinner A10 DRAM PLL
19 The first output is the DRAM clock output, the second is meant
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| D | allwinner,sun9i-a80-de-clks.yaml | 35 - const: dram
61 clock-names = "mod", "dram", "bus";
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| /Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra210-bpmp.txt | 6 (suspend to ram), and also offloading DRAM memory clock scaling on
23 - #clock-cells : Should be 1 for platforms where DRAM clock control is
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| D | qemu,fw-cfg-mmio.yaml | 21 DTB that QEMU places at the bottom of the guest's DRAM.
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,k3-m4f-rproc.yaml | 39 - description: DRAM internal memory region
44 - const: dram
115 reg-names = "iram", "dram";
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| /Documentation/driver-api/ |
| D | edac.rst | 18 The individual DRAM chips on a memory stick. These devices commonly
69 This is the name of the DRAM signal used to select the DRAM ranks to be
112 communication lanes. It uses vertically stacked memory chips (DRAM dies)
202 of 4096-bits of DRAM data bus.
204 While the UMC is interfacing a 16GB (8high X 2GB DRAM) HBM stack, each UMC
205 channel is interfacing 2GB of DRAM (represented as rank).
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| /Documentation/devicetree/bindings/mmc/ |
| D | amlogic,meson-gx-mmc.yaml | 48 amlogic,dram-access-quirk:
51 set when controller's internal DMA engine cannot access the DRAM memory,
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| /Documentation/hwmon/ |
| D | asus_wmi_sensors.rst | 37 * DRAM Voltage,
48 * DRAM Voltage,
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| /Documentation/admin-guide/perf/ |
| D | meson-ddr-pmu.rst | 7 The Amlogic Meson G12 SoC contains a bandwidth monitor inside DRAM controller.
9 DRAM. The channel can count up to 3 AXI port simultaneously. It can be helpful
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| /Documentation/devicetree/bindings/media/ |
| D | allwinner,sun4i-a10-csi.yaml | 39 - description: The CSI DRAM clock
44 - description: The CSI DRAM clock
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| D | nxp,imx8mq-mipi-csi2.yaml | 71 const: dram
147 interconnect-names = "dram";
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| /Documentation/devicetree/bindings/regulator/ |
| D | mediatek,mt6332-regulator.yaml | 19 "^buck-v(dram|dvfs2|pa|rf18a|rf18b|sbst)$":
25 pattern: "^v(dram|dvfs2|pa|rf18a|rf18b|sbst)$"
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| /Documentation/arch/arm/sa1100/ |
| D | lart.rst | 6 applications. It has 32 MB DRAM, 4MB Flash ROM, double RS232 and all
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| /Documentation/devicetree/bindings/edac/ |
| D | dmc-520.yaml | 13 DMC-520 node is defined to describe DRAM error detection and correction.
|