| /Documentation/devicetree/bindings/mmc/ |
| D | samsung,exynos-dw-mshc.yaml | 4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml#
19 - axis,artpec8-dw-mshc
20 - samsung,exynos4210-dw-mshc
21 - samsung,exynos4412-dw-mshc
22 - samsung,exynos5250-dw-mshc
23 - samsung,exynos5420-dw-mshc
24 - samsung,exynos5420-dw-mshc-smu
25 - samsung,exynos7-dw-mshc
26 - samsung,exynos7-dw-mshc-smu
29 - samsung,exynos5433-dw-mshc-smu
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| D | rockchip-dw-mshc.yaml | 4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
12 This file documents the combined properties for the core Synopsys dw mshc
13 controller that are not already included in the synopsys-dw-mshc-common.yaml
17 - $ref: synopsys-dw-mshc-common.yaml#
27 - const: rockchip,rk2928-dw-mshc
29 - const: rockchip,rk3288-dw-mshc
32 - rockchip,px30-dw-mshc
33 - rockchip,rk1808-dw-mshc
34 - rockchip,rk3036-dw-mshc
35 - rockchip,rk3128-dw-mshc
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| D | k3-dw-mshc.txt | 4 Read synopsys-dw-mshc.txt for more details
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
15 - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
16 - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
18 - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
19 - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
30 compatible = "hisilicon,hi4511-dw-mshc";
55 compatible = "hisilicon,hi6220-dw-mshc";
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| D | bluefield-dw-mshc.txt | 4 Read synopsys-dw-mshc.txt for more details
8 differences between the core Synopsys dw mshc controller properties described
9 by synopsys-dw-mshc.txt and the properties used by the Mellanox Bluefield SoC
15 - "mellanox,bluefield-dw-mshc": for controllers with Mellanox Bluefield SoC
22 compatible = "mellanox,bluefield-dw-mshc";
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| D | synopsys-dw-mshc.yaml | 4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml#
16 - altr,socfpga-dw-mshc
17 - img,pistachio-dw-mshc
18 - snps,dw-mshc
56 - $ref: synopsys-dw-mshc-common.yaml#
62 const: altr,socfpga-dw-mshc
83 compatible = "snps,dw-mshc";
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| D | hisilicon,hi3798cv200-dw-mshc.yaml | 4 $id: http://devicetree.org/schemas/mmc/hisilicon,hi3798cv200-dw-mshc.yaml#
15 - hisilicon,hi3798cv200-dw-mshc
16 - hisilicon,hi3798mv200-dw-mshc
55 - $ref: synopsys-dw-mshc-common.yaml#
61 const: hisilicon,hi3798mv200-dw-mshc
77 compatible = "hisilicon,hi3798cv200-dw-mshc";
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| D | microchip,dw-sparx5-sdhci.yaml | 4 $id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
18 const: microchip,dw-sparx5-sdhci
56 compatible = "microchip,dw-sparx5-sdhci";
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| /Documentation/devicetree/bindings/watchdog/ |
| D | snps,dw-wdt.yaml | 4 $id: http://devicetree.org/schemas/watchdog/snps,dw-wdt.yaml#
18 - const: snps,dw-wdt
35 - const: snps,dw-wdt
41 description: DW Watchdog pre-timeout interrupt
57 description: Phandle to the DW Watchdog reset lane
63 DW APB Watchdog custom timer intervals - Timeout Period ranges (TOPs).
67 the timer expiration intervals supported by the DW APB Watchdog. Note
68 DW APB Watchdog IP-core might be synthesized with fixed TOP values,
87 compatible = "snps,dw-wdt";
96 compatible = "snps,dw-wdt";
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-xdata | 1 What: /sys/class/misc/drivers/dw-xdata-pcie.<device>/write
13 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/write
15 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/write
21 cat /sys/class/misc/dw-xdata-pcie.<device>/write
26 What: /sys/class/misc/dw-xdata-pcie.<device>/read
38 echo 1 > /sys/class/misc/dw-xdata-pcie.<device>/read
40 echo 0 > /sys/class/misc/dw-xdata-pcie.<device>/read
46 cat /sys/class/misc/dw-xdata-pcie.<device>/read
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| /Documentation/devicetree/bindings/timer/ |
| D | snps,dw-apb-timer.yaml | 4 $id: http://devicetree.org/schemas/timer/snps,dw-apb-timer.yaml#
15 - const: snps,dw-apb-timer
17 - snps,dw-apb-timer-sp
18 - snps,dw-apb-timer-osc
63 compatible = "snps,dw-apb-timer";
71 compatible = "snps,dw-apb-timer";
79 compatible = "snps,dw-apb-timer";
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| /Documentation/devicetree/bindings/net/pcs/ |
| D | snps,dw-xpcs.yaml | 4 $id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
29 const: snps,dw-xpcs
31 const: snps,dw-xpcs-gen1-3g
33 const: snps,dw-xpcs-gen2-3g
35 const: snps,dw-xpcs-gen2-6g
37 const: snps,dw-xpcs-gen4-3g
39 const: snps,dw-xpcs-gen4-6g
41 const: snps,dw-xpcs-gen5-10g
43 const: snps,dw-xpcs-gen5-12g
49 of the MDIO bus device. If DW XPCS CSRs space is accessed over the
[all …]
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| /Documentation/devicetree/bindings/serial/ |
| D | snps-dw-apb-uart.yaml | 4 $id: http://devicetree.org/schemas/serial/snps-dw-apb-uart.yaml#
55 - const: snps,dw-apb-uart
58 - brcm,bcm11351-dw-apb-uart
59 - brcm,bcm21664-dw-apb-uart
60 - const: snps,dw-apb-uart
66 - const: snps,dw-apb-uart
67 - const: snps,dw-apb-uart
143 compatible = "snps,dw-apb-uart";
158 compatible = "snps,dw-apb-uart";
169 compatible = "snps,dw-apb-uart";
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| /Documentation/devicetree/bindings/pci/ |
| D | axis,artpec6-pcie.txt | 4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
27 compatible = "axis,artpec6-pcie", "snps,dw-pcie";
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| /Documentation/misc-devices/ |
| D | dw-xdata-pcie.rst | 22 The dw-xdata-pcie driver can be used to enable/disable PCIe traffic
38 # echo 1 > /sys/class/misc/dw-xdata-pcie.0/write
42 # cat /sys/class/misc/dw-xdata-pcie.0/write
47 # echo 0 > /sys/class/misc/dw-xdata-pcie.0/write
54 # echo 1 > /sys/class/misc/dw-xdata-pcie.0/read
58 # cat /sys/class/misc/dw-xdata-pcie.0/read
63 # echo 0 > /sys/class/misc/dw-xdata-pcie.0/read
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| /Documentation/devicetree/bindings/reset/ |
| D | snps,dw-reset.txt | 10 "snps,dw-high-reset" - for active high configuration
11 "snps,dw-low-reset" - for active low configuration
21 compatible = "snps,dw-high-reset";
27 compatible = "snps,dw-low-reset";
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| /Documentation/devicetree/bindings/display/ |
| D | allwinner,sun8i-a83t-dw-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/allwinner,sun8i-a83t-dw-hdmi.yaml#
15 in bridge/synopsys,dw-hdmi.yaml with the following device-specific
28 - const: allwinner,sun8i-a83t-dw-hdmi
29 - const: allwinner,sun50i-h6-dw-hdmi
33 - allwinner,sun8i-h3-dw-hdmi
34 - allwinner,sun8i-r40-dw-hdmi
35 - allwinner,sun50i-a64-dw-hdmi
36 - const: allwinner,sun8i-a83t-dw-hdmi
129 - allwinner,sun50i-h6-dw-hdmi
164 compatible = "allwinner,sun8i-a83t-dw-hdmi";
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| D | amlogic,meson-dw-hdmi.yaml | 5 $id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
52 - amlogic,meson-gxbb-dw-hdmi # GXBB (S905)
53 - amlogic,meson-gxl-dw-hdmi # GXL (S905X, S905D)
54 - amlogic,meson-gxm-dw-hdmi # GXM (S912)
55 - const: amlogic,meson-gx-dw-hdmi
57 - amlogic,meson-g12a-dw-hdmi # G12A (S905X2, S905Y2, S905D2)
129 compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | snps,dw-umctl2-ddrc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
19 For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a
27 description: Synopsys DW uMCTL2 DDR controller v3.80a
29 - description: Synopsys DW uMCTL2 DDR controller
30 const: snps,dw-umctl2-ddrc
36 DW uMCTL2 DDRC IP-core provides individual IRQ signal for each event":"
107 compatible = "snps,dw-umctl2-ddrc";
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| /Documentation/devicetree/bindings/gpio/ |
| D | snps,dw-apb-gpio.yaml | 4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
23 const: snps,dw-apb-gpio
38 - description: DW GPIO debounce reference clock source
54 const: snps,dw-apb-gpio-port
120 compatible = "snps,dw-apb-gpio";
126 compatible = "snps,dw-apb-gpio-port";
138 compatible = "snps,dw-apb-gpio-port";
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| /Documentation/devicetree/bindings/spi/ |
| D | snps,dw-apb-ssi.yaml | 4 $id: http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
55 - description: Generic DW SPI Controller
57 - snps,dw-apb-ssi
64 - const: snps,dw-apb-ssi
68 const: amazon,alpine-dw-apb-ssi
72 - const: snps,dw-apb-ssi
94 - const: snps,dw-apb-ssi
99 - description: DW APB SSI controller memory mapped registers
184 compatible = "snps,dw-apb-ssi";
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| /Documentation/devicetree/bindings/display/rockchip/ |
| D | rockchip,dw-hdmi.yaml | 4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
17 - $ref: ../bridge/synopsys,dw-hdmi.yaml#
23 - rockchip,rk3228-dw-hdmi
24 - rockchip,rk3288-dw-hdmi
25 - rockchip,rk3328-dw-hdmi
26 - rockchip,rk3399-dw-hdmi
27 - rockchip,rk3568-dw-hdmi
143 compatible = "rockchip,rk3288-dw-hdmi";
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| /Documentation/devicetree/bindings/pwm/ |
| D | snps,dw-apb-timers-pwm2.yaml | 5 $id: http://devicetree.org/schemas/pwm/snps,dw-apb-timers-pwm2.yaml#
8 title: Synopsys DW-APB timers PWM controller
28 const: snps,dw-apb-timers-pwm2
62 compatible = "snps,dw-apb-timers-pwm2";
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| /Documentation/devicetree/bindings/i3c/ |
| D | snps,dw-i3c-master.yaml | 4 $id: http://devicetree.org/schemas/i3c/snps,dw-i3c-master.yaml#
17 const: snps,dw-i3c-master-1.00a
48 compatible = "snps,dw-i3c-master-1.00a";
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | snps,dw-apb-ictl.txt | 9 - compatible: shall be "snps,dw-apb-ictl"
29 compatible = "snps,dw-apb-ictl";
39 compatible = "snps,dw-apb-ictl";
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | ingenic,jz4780-hdmi.yaml | 17 - $ref: synopsys,dw-hdmi.yaml#
21 const: ingenic,jz4780-dw-hdmi
55 compatible = "ingenic,jz4780-dw-hdmi";
|