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/Documentation/devicetree/bindings/usb/
Dqcom,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
16 - qcom,ipq4019-dwc3
17 - qcom,ipq5018-dwc3
18 - qcom,ipq5332-dwc3
19 - qcom,ipq6018-dwc3
20 - qcom,ipq8064-dwc3
21 - qcom,ipq8074-dwc3
22 - qcom,ipq9574-dwc3
23 - qcom,msm8953-dwc3
[all …]
Drealtek,rtd-dwc3.yaml5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
8 title: Realtek DWC3 USB SoC Controller Glue
14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
21 - realtek,rtd1295-dwc3
22 - realtek,rtd1315e-dwc3
23 - realtek,rtd1319-dwc3
24 - realtek,rtd1319d-dwc3
25 - realtek,rtd1395-dwc3
26 - realtek,rtd1619-dwc3
27 - realtek,rtd1619b-dwc3
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Drockchip,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
13 The common content of the node is defined in snps,dwc3.yaml.
28 - rockchip,rk3328-dwc3
29 - rockchip,rk3568-dwc3
30 - rockchip,rk3588-dwc3
38 - rockchip,rk3328-dwc3
39 - rockchip,rk3568-dwc3
40 - rockchip,rk3588-dwc3
41 - const: snps,dwc3
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Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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Dfsl,ls1028a.yaml7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
17 - fsl,ls1028a-dwc3
25 - fsl,ls1028a-dwc3
26 - const: snps,dwc3
42 - $ref: snps,dwc3.yaml#
49 compatible = "fsl,ls1028a-dwc3", "snps,dwc3";
Dfsl,imx8mq-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
18 - fsl,imx8mq-dwc3
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
29 - $ref: snps,dwc3.yaml#
39 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
Domap-usb.txt46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
71 compatible = "ti,dwc3";
Dti,keystone-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
61 $ref: snps,dwc3.yaml#
77 dwc3@2680000 {
78 compatible = "ti,keystone-dwc3";
87 compatible = "snps,dwc3";
Dintel,keembay-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml#
7 title: Intel Keem Bay DWC3 USB controller
14 const: intel,keembay-dwc3
41 $ref: snps,dwc3.yaml#
61 compatible = "intel,keembay-dwc3";
72 compatible = "snps,dwc3";
Dhisilicon,hi3798mv200-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/hisilicon,hi3798mv200-dwc3.yaml#
7 title: HiSilicon Hi3798MV200 DWC3 USB SoC controller
14 const: hisilicon,hi3798mv200-dwc3
52 $ref: snps,dwc3.yaml#
71 compatible = "hisilicon,hi3798mv200-dwc3";
87 compatible = "snps,dwc3";
Ddwc3-cavium.txt1 Cavium SuperSpeed DWC3 USB SoC controller
7 A child node must exist to represent the core DWC3 IP block. The name of
8 the node is not important. The content of the node is defined in dwc3.txt.
23 compatible = "cavium,octeon-7130-xhci", "snps,dwc3";
Ddwc3-xilinx.yaml4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
7 title: Xilinx SuperSpeed DWC3 USB SoC controller
17 - xlnx,zynqmp-dwc3
18 - xlnx,versal-dwc3
83 $ref: snps,dwc3.yaml#
114 compatible = "xlnx,zynqmp-dwc3";
128 compatible = "snps,dwc3";
Drockchip,rk3399-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
7 title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
14 const: rockchip,rk3399-dwc3
57 $ref: snps,dwc3.yaml#
82 compatible = "rockchip,rk3399-dwc3";
96 compatible = "snps,dwc3";
Damlogic,meson-g12a-usb-ctrl.yaml8 title: Amlogic Meson G12A DWC3 USB SoC Controller Glue
14 The Amlogic G12A embeds a DWC3 USB IP Core configured for USB2 and USB3
18 A glue connects the DWC3 core to USB2 PHYs and optionally to an USB3 PHY.
22 The DWC3 Glue controls the PHY routing and power, an interrupt line is
25 The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in
84 - $ref: snps,dwc3.yaml#
229 dwc3: usb@ff500000 {
230 compatible = "snps,dwc3";
Dfsl,imx8mp-dwc3.yaml5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
15 const: fsl,imx8mp-dwc3
20 - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
81 $ref: snps,dwc3.yaml#
103 compatible = "fsl,imx8mp-dwc3";
117 compatible = "snps,dwc3";
Dsnps,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/snps,dwc3.yaml#
13 This is usually a subnode to DWC3 glue to which it is connected, but can also
35 - const: snps,dwc3
36 - const: synopsys,dwc3
44 It's either a single common DWC3 interrupt (dwc_usb3) or individual
101 The DWC3 has 2 power-domains. The power management unit (PMU) and
139 description: True when DWC3 was configured with LPM Erratum enabled
279 True when DWC3 asserts output signal utmi_l1_suspend_n, false when
322 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed
338 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed
[all …]
Dsamsung,exynos-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/samsung,exynos-dwc3.yaml#
7 title: Samsung Exynos SoC USB 3.0 DWC3 Controller
45 $ref: snps,dwc3.yaml#
156 compatible = "snps,dwc3";
/Documentation/devicetree/bindings/soc/socionext/
Dsocionext,uniphier-dwc3-glue.yaml4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
25 - socionext,uniphier-pxs3-dwc3-glue
26 - socionext,uniphier-nx1-dwc3-glue
[all …]
/Documentation/devicetree/bindings/phy/
Dqcom,ipq806x-usb-phy-hs.yaml7 title: Qualcomm ipq806x usb DWC3 HS PHY CONTROLLER
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
Dqcom,ipq806x-usb-phy-ss.yaml7 title: Qualcomm ipq806x usb DWC3 SS PHY CONTROLLER
13 DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
14 controllers used in ipq806x. Each DWC3 PHY controller should have its
/Documentation/driver-api/usb/
Ddwc3.rst12 (hereinafter referred to as *DWC3*) is a USB SuperSpeed compliant
40 For details about features supported by your version of DWC3, consult
65 The DWC3 driver sits on the *drivers/usb/dwc3/* directory. All files
69 Because of DWC3's configuration flexibility, the driver is a little
78 Like any other HW, DWC3 has its own set of limitations. To avoid
90 512 on HighSpeed, etc), or DWC3 driver must add a Chained TRB pointing
94 Note that as of this writing, this won't be a problem because DWC3 is
98 about DWC3 and *non-working transfers*.
108 DWC3 driver will try its best to cope with more than 255 requests and,
116 Whenever you encounter a problem with DWC3, first and foremost you
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Dindex.rst19 dwc3
/Documentation/usb/
Ddwc3.rst2 DWC3 driver
13 As it turns out some DWC3-commands ~1ms to complete. Currently we spin
Dindex.rst11 dwc3
/Documentation/devicetree/bindings/soc/qcom/
Dqcom,eud.yaml35 These ports is to be attached to the endpoint of the DWC3 controller node
42 description: This port is to be attached to the DWC3 controller.

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