Searched full:decode (Results 1 – 25 of 94) sorted by relevance
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| /Documentation/userspace-api/media/v4l/ |
| D | pixfmt-compressed.rst | 70 In addition, metadata associated with the frame to decode are
79 appropriate number of macroblocks to decode a full
121 Metadata associated with the frame to decode is required to be passed
129 of macroblocks to decode a full corresponding frame to the matching
165 Metadata associated with the frame to decode is required to be passed
170 of macroblocks to decode a full corresponding frame to the matching
187 Metadata associated with the frame to decode is required to be passed
193 of macroblocks to decode a full corresponding frame to the matching
215 Metadata associated with the frame to decode is required to be passed
222 number of macroblocks to decode a full corresponding frame.
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| D | dev-stateless-decoder.rst | 19 with stateless decoders in order to successfully decode an encoded stream.
30 frame may be the result of several decode requests (for instance, H.264 streams
59 that may not be usable for the media the client is trying to decode.
238 * All the metadata needed to decode the submitted encoded data, in the form of
247 decode requests after the current one in order to be produced, then the client
250 buffer not being made available for dequeueing, and reused for the next decode
271 we are not sure that the current decode request is the last one needed
281 as the reference of another. If using multiple decode requests per
300 array must contain all the codec-specific controls required to decode
325 independently. They are returned in decode order (i.e. the same order as coded
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| D | dev-decoder.rst | 81 decode order
84 ``OUTPUT`` buffers must be queued by the client in decode order; for
85 encoders ``CAPTURE`` buffers must be returned by the encoder in decode order.
88 data resulting from the decode process; see ``CAPTURE``.
132 SPS/PPS/IDR sequence (H.264/HEVC); a resume point is required to start decode
367 * If data in a buffer that triggers the event is required to decode the
729 preceded it in decode, but succeeded it in the display order),
732 ``CAPTURE`` later into decode process, and/or after processing further
776 decode a new frame into it while it is still in use, resulting in corruption
799 * the CAPTURE buffer that contains the results of the failed decode operation
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| /Documentation/admin-guide/RAS/ |
| D | error-decoding.rst | 12 While the daemon is running, it would automatically log and decode
13 errors. If not, one can still decode such errors by supplying the
18 Also, the user can pass particular family and model to decode the error
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| /Documentation/driver-api/cxl/ |
| D | memory-devices.rst | 21 assemble them into a CXL.mem decode topology. The need for runtime configuration
29 (Linux term for the top of the CXL decode topology). From there, PCIe topology
30 dictates which endpoints can participate in which Host Bridge decode regimes.
184 'struct cxl_port' object. A 'cxl_port' is a device that can decode CXL.mem to
185 its descendants. So "root" claims non-PCIe enumerable platform decode ranges and
186 decodes them to "ports", "ports" decode to "endpoints", and "endpoints"
187 represent the decode from SPA (System Physical Address) to DPA (Device Physical
200 The port metadata and potential decode schemes that a give memory device may
250 device name of 'mem3' which platform level decode ranges may this device
259 decode scheme can be determined via a command like the following::
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| /Documentation/devicetree/bindings/media/ |
| D | mediatek,vcodec-subdev-decoder.yaml | 8 title: Mediatek Video Decode Accelerator With Multi Hardware
14 Mediatek Video Decode is the video decode hardware present in Mediatek
40 then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode
41 done. Core workqueue need to get lat buffer and output buffer, then enable core to decode,
42 writing the result to output buffer, disable hardware when core decode done. These two
43 hardwares will decode each frame cyclically.
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| D | qcom,venus-common.yaml | 7 title: Qualcomm SoC Venus Video Encode and Decode Accelerators Common Properties
14 The Venus IP is a video encode and decode accelerator present
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| D | qcom,msm8916-venus.yaml | 7 title: Qualcomm MSM8916 Venus video encode and decode accelerators
13 The Venus IP is a video encode and decode accelerator present
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| D | qcom,sc7180-venus.yaml | 7 title: Qualcomm SC7180 Venus video encode and decode accelerators
13 The Venus IP is a video encode and decode accelerator present
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| D | mediatek,vcodec-decoder.yaml | 8 title: Mediatek Video Decode Accelerator
14 Mediatek Video Decode is the video decode hardware present in Mediatek
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| D | qcom,sdm845-venus.yaml | 7 title: Qualcomm SDM845 Venus video encode and decode accelerators
13 The Venus IP is a video encode and decode accelerator present
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| D | qcom,sdm845-venus-v2.yaml | 7 title: Qualcomm SDM845 Venus v2 video encode and decode accelerators
13 The Venus IP is a video encode and decode accelerator present
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| D | qcom,sm8250-venus.yaml | 7 title: Qualcomm SM8250 Venus video encode and decode accelerators
13 The Venus IP is a video encode and decode accelerator present
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| D | qcom,sc7280-venus.yaml | 7 title: Qualcomm SC7280 Venus video encode and decode accelerators
13 The Venus Iris2 IP is a video encode and decode accelerator present
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| D | amlogic,gx-vdec.yaml | 22 - VDEC_1 can decode MPEG-1, MPEG-2, MPEG-4 part 2, MJPEG, H.263, H.264, VC-1.
23 - VDEC_HEVC can decode HEVC and VP9.
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| D | qcom,sdm660-venus.yaml | 7 title: Qualcomm SDM660 Venus video encode and decode accelerators
14 The Venus IP is a video encode and decode accelerator present
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| D | qcom,msm8996-venus.yaml | 7 title: Qualcomm MSM8996 Venus video encode and decode accelerators
13 The Venus IP is a video encode and decode accelerator present
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| D | microchip,sama5d4-vdec.yaml | 14 Hantro G1 video decode accelerator present on Microchip SAMA5D4 SoCs.
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| D | mediatek-vpu.txt | 4 H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert).
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| /Documentation/misc-devices/ |
| D | xilinx_sdfec.rst | 49 - Load the configuration parameters for either Turbo decode or LDPC encode or decode
58 the Turbo decode or LDPC encode or decode. The role of the driver is to allow
111 - Set Turbo decode, LPDC encode or decode parameters, depending on how the
161 Set Turbo Decode
164 Configuring the Turbo decode parameters is done by using the ioctl :c:macro:`XSDFEC_SET_TURBO` usin…
166 Adding Turbo decode can only be done if the following restrictions are met:
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| /Documentation/arch/x86/x86_64/ |
| D | machinecheck.rst | 15 mcelog knows how to decode them.
18 log then mcelog should run to collect and decode machine check entries
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-event_source-devices-hv_gpci | 102 * The end user reading this sysfs file must decode the content as per
134 * The end user reading this sysfs file must decode the content as per
166 * The end user reading this sysfs file must decode the content as per
198 * The end user reading this sysfs file must decode the content as per
230 * The end user reading this sysfs file must decode the content as per
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| D | sysfs-bus-cxl | 210 may target in its decode of CXL memory resources. The 'Y'
250 decoder's decode window. For decoders of devtype
253 decode range of the cxl_port ancestor of the decoder's cxl_port,
301 can optionally decode either accelerator memory (type-2) or
304 memory regions are activated in this decode hierarchy.
390 space this decoder claims at address N before the decode rotates
403 (interleave-set) within the decode range bounded by root decoder
517 to map decode scenario, like the endpoint is unreachable at that
523 successfully written a final validation for decode conflicts is
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| /Documentation/gpu/amdgpu/ |
| D | debugging.rst | 20 If you see a GPU page fault in the kernel log, you can decode it to figure
57 - VCN: Video encode/decode engines
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| /Documentation/driver-api/media/ |
| D | rc-core.rst | 57 microcontroller that decode the *PULSE/SPACE* sequence and return scan
69 receivers, it needs to decode the IR protocol, in order to obtain the
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