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/Documentation/devicetree/bindings/pci/
Dhost-generic-pci.yaml31 While ECAM extends this by 4 bits to accommodate 4k of function space:
38 description: Depends on the layout of configuration space (CAM vs ECAM
46 - const: pci-host-ecam-generic
51 some Cavium ThunderX processors. These devices have ECAM-based config
55 const: cavium,pci-host-thunder-ecam
60 HiSilicon Hip06/Hip07 PCIe host bridge in almost-ECAM mode. Some
61 firmware places the host controller in a mode where it is ECAM
64 - hisilicon,hip06-pcie-ecam
65 - hisilicon,hip07-pcie-ecam
69 that cover all config, MMIO and I/O spaces in a [mostly] ECAM
[all …]
Dpcie-al.txt25 - "config" PCIe ECAM space
Dnvidia,tegra194-pcie.yaml39 - description: aperture to access the configuration space through ECAM.
48 - const: ecam
338 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
339 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
Dpci.txt77 compatible = "pci-host-ecam-generic";
Dapple,pcie.yaml20 All root ports share a single ECAM space, but separate GPIOs are
Dsnps,dw-pcie.yaml115 enum: [ ecam ]
/Documentation/PCI/
Dacpi-info.rst52 the device-specific details. The host bridge registers also include ECAM
66 bridge registers (including ECAM space) in PNP0C02 catch-all devices [6].
67 With the exception of ECAM, the bridge register space is device-specific
72 descriptors in the PNP0A03 device for bridge registers, including ECAM,
84 The PCIe spec requires the Enhanced Configuration Access Method (ECAM)
86 ia64 SAL interface [7]. A host bridge consumes ECAM memory address space
88 defines the ECAM address space layout and functionality; only the base of
92 The MCFG table must describe the ECAM space of non-hot pluggable host
94 a _CBA method in the PNP0A03 device describes the ECAM space of a
167 access to the Configuration Space, the ECAM is required as defined in
/Documentation/translations/zh_CN/PCI/
Dacpi-info.rst60 ECAM，尽管对[6]的严格解释可能禁止这样做。旧的x86和ia64内核假定所有的地址空间描述
69 型配置访问方法（ECAM）。主桥消耗ECAM内存地址空间并将内存访问转换为PCI配置访问。该规范