Searched full:emc (Results 1 – 25 of 30) sorted by relevance
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | nvidia,tegra124-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
30 - const: emc
51 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-config:
77 nvidia,emc-auto-cal-config2:
83 nvidia,emc-auto-cal-config3:
89 nvidia,emc-auto-cal-interval:
96 nvidia,emc-bgbias-ctl0:
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| D | nvidia,tegra20-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
18 parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
23 const: nvidia,tegra20-emc
61 If present, the emc-tables@ sub-nodes will be addressed.
64 emc-table:
68 const: nvidia,tegra20-emc-table
82 nvidia,emc-registers:
84 EMC timing characterization data. These are the registers
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| D | nvidia,tegra30-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
23 const: nvidia,tegra30-emc
53 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-interval:
78 nvidia,emc-mode-1:
83 nvidia,emc-mode-2:
88 nvidia,emc-mode-reset:
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| D | nvidia,tegra210-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra210-emc
30 - const: emc
34 - description: EMC general interrupt
39 phandle to a reserved memory region describing the table of EMC
66 emc_table: emc-table@83400000 {
67 compatible = "nvidia,tegra210-emc-table";
73 compatible = "nvidia,tegra210-emc";
78 clock-names = "emc";
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| D | nvidia,tegra186-mc.yaml | 66 coprocessor exposes the EMC clock that is used to set the frequency at
74 - nvidia,tegra186-emc
75 - nvidia,tegra194-emc
76 - nvidia,tegra234-emc
84 - description: EMC general interrupt
92 - const: emc
106 const: nvidia,tegra186-emc
115 const: nvidia,tegra194-emc
124 const: nvidia,tegra234-emc
265 compatible = "nvidia,tegra186-emc";
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| D | nvidia,tegra124-mc.yaml | 47 "^emc-timings-[0-9]+$":
128 emc-timings-3 {
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| D | nvidia,tegra30-mc.yaml | 64 "^emc-timings-[0-9]+$":
144 emc-timings-1 {
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| D | arm,pl172.txt | 90 emc: memory-controller@40005000 {
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| /Documentation/devicetree/bindings/reserved-memory/ |
| D | nvidia,tegra210-emc-table.yaml | 4 $id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra210-emc-table.yaml#
7 title: NVIDIA Tegra210 EMC Frequency Table
14 EMC frequency table via a reserved memory region.
21 const: nvidia,tegra210-emc-table
24 description: region of memory reserved by firmware to pass the EMC
|
| /Documentation/devicetree/bindings/display/tegra/ |
| D | nvidia,tegra186-display.yaml | 159 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
160 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
178 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
179 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
197 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
198 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
247 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
248 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
265 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
266 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
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| /Documentation/devicetree/bindings/devfreq/ |
| D | nvidia,tegra30-actmon.yaml | 37 - const: emc
101 emc: external-memory-controller@7000f400 {
102 compatible = "nvidia,tegra30-emc";
119 clock-names = "actmon", "emc";
123 interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
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| /Documentation/devicetree/bindings/firmware/ |
| D | nvidia,tegra186-bpmp.yaml | 175 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
176 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
177 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
178 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
205 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
206 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
207 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
208 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
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| /Documentation/devicetree/bindings/clock/ |
| D | nvidia,tegra124-car.yaml | 49 "^emc-timings-[0-9]+$":
77 - description: parent clock of EMC
81 - const: emc-parent
|
| /Documentation/devicetree/bindings/gpu/host1x/ |
| D | nvidia,tegra210-nvdec.yaml | 101 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
102 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
103 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
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| D | nvidia,tegra210-nvjpg.yaml | 90 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
91 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;
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| D | nvidia,tegra210-nvenc.yaml | 131 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
132 <&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
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| D | nvidia,tegra234-nvdec.yaml | 141 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
142 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
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| /Documentation/ABI/testing/ |
| D | sysfs-firmware-efi | 36 Table version 2 on Dell EMC PowerEdge systems in binary format
37 Users: It is used by Dell EMC OpenManage Server Administrator tool to
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| /Documentation/devicetree/bindings/net/ |
| D | nvidia,tegra234-mgbe.yaml | 142 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
143 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
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| /Documentation/devicetree/bindings/usb/ |
| D | nvidia,tegra234-xusb.yaml | 146 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
147 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
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| D | nvidia,tegra186-xusb.yaml | 160 interconnects = <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTR &emc>,
161 <&mc TEGRA186_MEMORY_CLIENT_XUSB_HOSTW &emc>;
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| D | nvidia,tegra194-xusb.yaml | 161 interconnects = <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTR &emc>,
162 <&mc TEGRA194_MEMORY_CLIENT_XUSB_HOSTW &emc>;
|
| /Documentation/devicetree/bindings/reset/ |
| D | nxp,lpc1850-rgu.txt | 27 21 External memory controller (EMC)
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| /Documentation/devicetree/bindings/arm/tegra/ |
| D | nvidia,tegra186-pmc.yaml | 209 interconnects = <&mc TEGRA186_MEMORY_CLIENT_SDMMCRA &emc>,
210 <&mc TEGRA186_MEMORY_CLIENT_SDMMCWA &emc>;
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| /Documentation/devicetree/bindings/regulator/ |
| D | mt6359-regulator.yaml | 38 "^ldo_v(rfck|emc|a12|a09|ufs|bbck)$":
44 pattern: "^v(rfck|emc|a12|a09|ufs|bbck)$"
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