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/Documentation/devicetree/bindings/phy/
Dmediatek,tphy.yaml23 0x0100 FMREG
40 0x0100 FMREG
49 0x1100 FMREG
60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back
62 added on V2; the FMREG bank for slew rate calibration is not used anymore
Dmediatek,xsphy.yaml21 0x0100 FMREG
24 0x1100 FMREG