| /Documentation/devicetree/bindings/fpga/ |
| D | fpga-region.yaml | 4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
7 title: FPGA Region
17 - FPGA Region
25 FPGA Regions represent FPGA's and partial reconfiguration regions of FPGA's in
26 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
29 The documentation hits some of the high points of FPGA usage and
30 attempts to include terminology used by both major FPGA manufacturers. This
31 document isn't a replacement for any manufacturers specifications for FPGA
39 * The entire FPGA is programmed.
42 * A section of an FPGA is reprogrammed while the rest of the FPGA is not
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| D | lattice-machxo2-spi.txt | 1 Lattice MachXO2 Slave SPI FPGA Manager
10 - reg: spi chip select of the FPGA
12 Example for full FPGA configuration:
14 fpga-region0 {
15 compatible = "fpga-region";
16 fpga-mgr = <&fpga_mgr_spi>;
24 fpga_mgr_spi: fpga-mgr@0 {
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| D | xlnx,versal-fpga.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
7 title: Xilinx Versal FPGA driver.
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
20 - xlnx,versal-fpga
29 versal_fpga: versal-fpga {
30 compatible = "xlnx,versal-fpga";
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| D | altera-socfpga-fpga-mgr.txt | 1 Altera SOCFPGA FPGA Manager
4 - compatible : should contain "altr,socfpga-fpga-mgr"
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
8 - interrupts : interrupt for the FPGA Manager device.
13 compatible = "altr,socfpga-fpga-mgr";
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| D | altera-socfpga-a10-fpga-mgr.txt | 1 Altera SOCFPGA Arria10 FPGA Manager
4 - compatible : should contain "altr,socfpga-a10-fpga-mgr"
6 - The first index is for FPGA manager register access.
7 - The second index is for writing FPGA configuration data.
13 fpga_mgr: fpga-mgr@ffd03000 {
14 compatible = "altr,socfpga-a10-fpga-mgr";
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| D | altera-passive-serial.txt | 1 Altera Passive Serial SPI FPGA Manager
12 "altr,fpga-passive-serial",
13 "altr,fpga-arria10-passive-serial"
14 - reg: SPI chip select of the FPGA
22 fpga: fpga@0 {
23 compatible = "altr,fpga-passive-serial";
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| D | lattice-ice40-fpga-mgr.txt | 1 Lattice iCE40 FPGA Manager
4 - compatible: Should contain "lattice,ice40-fpga-mgr"
10 FPGA will enter Master SPI mode and drive SCK with a
15 fpga: fpga@0 {
16 compatible = "lattice,ice40-fpga-mgr";
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| D | intel-stratix10-soc-fpga-mgr.txt | 1 Intel Stratix10 SoC FPGA Manager
7 - compatible : should contain "intel,stratix10-soc-fpga-mgr" or
8 "intel,agilex-soc-fpga-mgr"
14 fpga_mgr: fpga-mgr {
15 compatible = "intel,stratix10-soc-fpga-mgr";
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| D | xlnx,zynqmp-pcap-fpga.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
20 const: xlnx,zynqmp-pcap-fpga
32 compatible = "xlnx,zynqmp-pcap-fpga";
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| D | xlnx,fpga-selectmap.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml#
7 title: Xilinx SelectMAP FPGA interface
27 - xlnx,fpga-xc7s-selectmap
28 - xlnx,fpga-xc7a-selectmap
29 - xlnx,fpga-xc7k-selectmap
30 - xlnx,fpga-xc7v-selectmap
77 fpga-mgr@8000000 {
78 compatible = "xlnx,fpga-xc7s-selectmap";
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| D | microchip,mpf-spi-fpga-mgr.yaml | 4 $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
7 title: Microchip Polarfire FPGA manager.
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
19 - microchip,mpf-spi-fpga-mgr
41 compatible = "microchip,mpf-spi-fpga-mgr";
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| D | fpga-bridge.yaml | 4 $id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#
7 title: FPGA Bridge
14 pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"
28 fpga-bridge {
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| D | xlnx,fpga-slave-serial.yaml | 4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
7 title: Xilinx Slave Serial SPI FPGA
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
29 - xlnx,fpga-slave-serial
70 fpga_mgr_spi: fpga-mgr@0 {
71 compatible = "xlnx,fpga-slave-serial";
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| /Documentation/driver-api/fpga/ |
| D | fpga-region.rst | 1 FPGA Region
7 This document is meant to be a brief overview of the FPGA region API usage. A
12 an FPGA Manager and a bridge (or bridges) with a reprogrammable region of an
13 FPGA or the whole FPGA. The API provides a way to register a region and to
16 Currently the only layer above fpga-region.c in the kernel is the Device Tree
17 support (of-fpga-region.c) described in [#f1]_. The DT support layer uses regions
18 to program the FPGA and then DT to handle enumeration. The common region code
22 An fpga-region can be set up to know the following things:
24 * which FPGA manager to use to do the programming
28 Additional info needed to program the FPGA image is passed in the struct
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| D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
5 Linux. Some of the core intentions of the FPGA subsystems are:
7 * The FPGA subsystem is vendor agnostic.
9 * The FPGA subsystem separates upper layers (userspace interfaces and
11 FPGA.
16 other users. Write the linux-fpga mailing list and maintainers and
23 FPGA Manager
26 If you are adding a new FPGA or a new method of programming an FPGA,
27 this is the subsystem for you. Low level FPGA manager drivers contain
29 includes the framework in fpga-mgr.c and the low level drivers that
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| D | fpga-programming.rst | 1 In-kernel API for FPGA Programming
7 The in-kernel API for FPGA programming is a combination of APIs from
8 FPGA manager, bridge, and regions. The actual function used to
9 trigger FPGA programming is fpga_region_program_fpga().
12 the FPGA manager and bridges. It will:
15 * lock the mutex of the region's FPGA manager
16 * build a list of FPGA bridges if a method has been specified to do so
18 * program the FPGA using info passed in :c:expr:`fpga_region->info`.
22 The struct fpga_image_info specifies what FPGA image to program. It is
26 How to program an FPGA using a region
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| D | fpga-mgr.rst | 1 FPGA Manager
7 The FPGA manager core exports a set of functions for programming an FPGA with
10 The FPGA image data itself is very manufacturer specific, but for our purposes
11 it's just binary data. The FPGA manager core won't parse it.
13 The FPGA image to be programmed can be in a scatter gather list, a single
20 FPGA image as well as image-specific particulars such as whether the image was
23 How to support a new FPGA device
26 To add another FPGA manager, write a driver that implements a set of ops. The
53 mgr = fpga_mgr_register(dev, "Altera SOCFPGA FPGA Manager",
80 do the programming sequence for this particular FPGA. These ops return 0 for
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| D | fpga-bridge.rst | 1 FPGA Bridge
4 API to implement a new FPGA bridge
7 * struct fpga_bridge - The FPGA Bridge structure
13 the module that registers the FPGA bridge as the owner.
15 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
18 .. kernel-doc:: include/linux/fpga/fpga-bridge.h
21 .. kernel-doc:: drivers/fpga/fpga-bridge.c
24 .. kernel-doc:: drivers/fpga/fpga-bridge.c
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| D | index.rst | 2 FPGA Subsystem
11 fpga-mgr
12 fpga-bridge
13 fpga-region
14 fpga-programming
|
| /Documentation/ABI/testing/ |
| D | sysfs-class-fpga-manager | 1 What: /sys/class/fpga_manager/<fpga>/name
5 Description: Name of low level fpga manager driver.
7 What: /sys/class/fpga_manager/<fpga>/state
11 Description: Read fpga manager state as a string.
13 wrong during FPGA programming (something that the driver can't
18 This is a superset of FPGA states and fpga manager driver
19 states. The fpga manager driver is walking through these steps
20 to get the FPGA into a known operating state. It's a sequence,
21 though some steps may get skipped. Valid FPGA states will vary
25 * power off = FPGA power is off
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| /Documentation/devicetree/bindings/board/ |
| D | fsl,fpga-qixis.yaml | 4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
7 title: Freescale on-board FPGA/CPLD
16 - const: fsl,p1022ds-fpga
17 - const: fsl,fpga-ngpixis
20 - fsl,ls1088aqds-fpga
21 - fsl,ls1088ardb-fpga
22 - fsl,ls2080aqds-fpga
23 - fsl,ls2080ardb-fpga
24 - const: fsl,fpga-qixis
27 - fsl,ls1043aqds-fpga
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| D | fsl,fpga-qixis-i2c.yaml | 4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
7 title: Freescale on-board FPGA connected on I2C bus
17 - fsl,bsc9132qds-fpga
18 - const: fsl,fpga-qixis-i2c
21 - fsl,ls1028aqds-fpga
22 - fsl,lx2160aqds-fpga
23 - const: fsl,fpga-qixis-i2c
48 compatible = "fsl,bsc9132qds-fpga", "fsl,fpga-qixis-i2c";
59 compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
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| /Documentation/driver-api/ |
| D | xillybus.rst | 2 Xillybus driver for generic FPGA interface
22 -- Host never reads from the FPGA
37 An FPGA (Field Programmable Gate Array) is a piece of logic hardware, which
48 level, even lower than assembly language. In order to allow FPGA designers to
51 FPGA parallels of library functions. IP cores may implement certain
57 One of the daunting tasks in FPGA design is communicating with a fullblown
60 (registers, interrupts, DMA etc.) is a project in itself. When the FPGA's
62 make sense to design the FPGA's interface logic specifically for the project.
63 A special driver is then written to present the FPGA as a well-known interface
65 FPGA differently than any device on the bus.
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| /Documentation/devicetree/bindings/bus/ |
| D | ts-nbus.txt | 4 Systems FPGA on the TS-4600 SoM.
10 - pwms : The PWM bound to the FPGA
11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
16 - ts,rdy-gpios : The GPIO pin connected to the rdy line on the FPGA
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,versatile-fpga-irq.txt | 1 * ARM Versatile FPGA interrupt controller
3 One or more FPGA IRQ controllers can be synthesized in an ARM reference board
9 - compatible: "arm,versatile-fpga-irq"
12 as the FPGA IRQ controller has no configuration options for interrupt
14 - reg: The register bank for the FPGA interrupt controller.
27 compatible = "arm,versatile-fpga-irq";
36 - interrupts: if the FPGA IRQ controller is cascaded, i.e. if its IRQ
|