Searched full:fpgas (Results 1 – 22 of 22) sorted by relevance
| /Documentation/driver-api/fpga/ |
| D | intro.rst | 4 The FPGA subsystem supports reprogramming FPGAs dynamically under
54 reprogramming FPGAs when device tree overlays are applied.
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| /Documentation/devicetree/bindings/mfd/ |
| D | atmel-smc.txt | 5 devices like FPGAs).
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| /Documentation/devicetree/bindings/fpga/ |
| D | lattice-machxo2-spi.txt | 3 Lattice MachXO2 FPGAs support a method of loading the bitstream over
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| D | altera-passive-serial.txt | 3 Altera FPGAs support a method of loading the bitstream over what is
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| D | xlnx,fpga-selectmap.yaml | 13 Xilinx 7 Series FPGAs support a method of loading the bitstream over a
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| D | xlnx,fpga-slave-serial.yaml | 13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
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| D | fpga-region.yaml | 26 the Device Tree. FPGA Regions provide a way to program FPGAs under device tree
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| /Documentation/arch/nios2/ |
| D | nios2.rst | 18 Altera family of FPGAs. In order to support Linux, Nios II needs to be configured
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-altera.txt | 3 * in Altera's FPGAs.
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | xilinx-xadc.txt | 6 The Xilinx XADC is an ADC that can be found in the Series 7 FPGAs from Xilinx.
15 UltraScale+ FPGAs from Xilinx. The System Monitor provides a DRP interface for
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| /Documentation/devicetree/bindings/hwmon/ |
| D | maxim,max6639.yaml | 17 transistors, typically available in CPUs, FPGAs, or GPUs.
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| /Documentation/devicetree/bindings/ |
| D | xilinx.txt | 4 in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
107 The Xilinx SystemACE device is used to program FPGAs from an FPGA
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | csky,apb-intc.txt | 8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
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| /Documentation/devicetree/bindings/memory-controllers/fsl/ |
| D | fsl,ifc.yaml | 66 like FPGAs, CPLDs, etc.
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-mmio.yaml | 16 FPGAs or ASICs. Commonly, these controllers are accessed over memory-mapped
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| /Documentation/driver-api/gpio/ |
| D | intro.rst | 27 several dozen of them. Programmable logic devices (like FPGAs) can easily
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| /Documentation/driver-api/ |
| D | xillybus.rst | 40 or even a processor with its peripherals. FPGAs are the LEGO of hardware:
43 available on the market as a chipset, so FPGAs are mostly used when some
47 The challenge with FPGAs is that everything is implemented at a very low
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| D | ptp.rst | 123 …t PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs)
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | ti-aemif.txt | 58 There might be board specific devices like FPGAs.
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| /Documentation/devicetree/bindings/display/ |
| D | xylon,logicvc-display.yaml | 16 with Xilinx Zynq-7000 SoCs and Xilinx FPGAs.
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| /Documentation/ABI/testing/ |
| D | sysfs-class-cxl | 200 that support loadable PSLs. For FPGAs this field identifies
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| /Documentation/arch/powerpc/ |
| D | cxl.rst | 9 coherent connection of accelerators (FPGAs and other devices) to a
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