Searched full:fpu (Results 1 – 13 of 13) sorted by relevance
| /Documentation/core-api/ |
| D | floating-point.rst | 24 both with and without a floating-point unit, FPU availability must be checked
28 ``linux/fpu.h``, as described below. Some other architectures implement their
55 The runtime API is provided in ``linux/fpu.h``. This header cannot be included
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| /Documentation/locking/ |
| D | preempt-locking.rst | 46 switch. For example, on x86, entering and exiting FPU mode is now a critical
49 Remember, the kernel does not save FPU state except for user tasks. Therefore,
50 upon preemption, the FPU registers will be sold to the lowest bidder. Thus,
53 Note, some FPU functions are already explicitly preempt safe. For example,
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| /Documentation/arch/arm/stm32/ |
| D | stm32f429-overview.rst | 11 - ARM Cortex-M4 up to 180MHz with FPU
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| /Documentation/arch/x86/i386/ |
| D | IO-APIC.rst | 31 13: 1 XT-PIC fpu
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| /Documentation/arch/powerpc/ |
| D | elf_hwcaps.rst | 42 FPU, VMX, VSX, it is not necessary to test those HWCAPs, and it may be
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| /Documentation/kernel-hacking/ |
| D | hacking.rst | 134 The FPU context is not saved; even in user context the FPU state
136 with some user process' FPU state. If you really want to do this,
137 you would have to explicitly save/restore the full FPU state (and
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,vexpress-juno.yaml | 52 in a test chip on the core tile. It is intended to evaluate NEON, FPU
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| /Documentation/arch/parisc/ |
| D | registers.rst | 18 CR10 (CCR) lazy FPU saving*
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| /Documentation/translations/it_IT/kernel-hacking/ |
| D | hacking.rst | 151 Il contesto della FPU non è salvato; anche se siete in contesto utente
152 lo stato dell'FPU probabilmente non corrisponde a quello del processo
155 lo stato dell'FPU (ed evitare cambi di contesto). Generalmente è una
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| /Documentation/arch/loongarch/ |
| D | introduction.rst | 58 LoongArch has 32 FPRs ( ``$f0`` ~ ``$f31`` ) when FPU is present. Each one is
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 2043 the FPU and the NaN encoding requested with the value
2051 supported by the FPU
2053 by the FPU
2055 by the FPU
2057 supported by the FPU
2058 emulated accept any binaries but enable FPU emulator
2059 if binary mode is unsupported by the FPU.
2061 The FPU emulator is always able to support both NaN
2062 encodings, so if no FPU hardware is present or it has
3975 nofpu [MIPS,SH] Disable hardware FPU at boot time.
[all …]
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| /Documentation/virt/kvm/ |
| D | api.rst | 2739 MIPS FPU registers (see KVM_REG_MIPS_FPR_{32,64}() above) have the following
2741 always accessed according to the current guest FPU mode (Status.FR and
2743 if the guest FPU mode is changed. MIPS SIMD Architecture (MSA) vector
2745 overlap the FPU registers::
2747 0x7020 0000 0003 00 <0:3> <reg:5> (32-bit FPU registers)
2748 0x7030 0000 0003 00 <0:3> <reg:5> (64-bit FPU registers)
2751 MIPS FPU control registers (see KVM_REG_MIPS_FCR_{IR,CSR} above) have the
7349 allows the Config1.FP bit to be set to enable the FPU in the guest. Once this is
7351 accessed (depending on the current guest FPU register mode), and the Status.FR,
7353 depending on them being supported by the FPU.
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| /Documentation/filesystems/ |
| D | proc.rst | 776 13: 1 XT-PIC fpu
794 13: 0 0 XT-PIC fpu
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