Searched full:gicv3 (Results 1 – 18 of 18) sorted by relevance
| /Documentation/virt/kvm/devices/ |
| D | arm-vgic-its.rst | 11 optional. Creating a virtual ITS controller also requires a host GICv3 (see
26 Base address in the guest physical address space of the GICv3 ITS
66 The GICV3 must be restored before the ITS and all ITS registers but
73 The expected ordering when restoring the GICv3/ITS is described in section
147 Revision 0 of the ABI only supports the features of a virtual GICv3, and does
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| D | arm-vgic-v3.rst | 14 possible to create both a GICv3 and GICv2 on the same VM.
16 Creating a guest GICv3 device requires a host GICv3 as well.
24 Base address in the guest physical address space of the GICv3 distributor
29 Base address in the guest physical address space of the GICv3
103 in the GICv3/4 specs. Getting or setting such a register has the same
154 rules are documented in the GICv3 specification descriptions of the ICPENDR
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| D | arm-vgic.rst | 16 GICv3 implementations with hardware compatibility support allow creating a
17 guest GICv2 through this interface. For information on creating a guest GICv3
19 create both a GICv3 and GICv2 device on the same VM.
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | booting.txt | 191 对于拥有 GICv3 中断控制器并以 v3 模式运行的系统：
198 - 设备树（DT）或 ACPI 表必须描述一个 GICv3 中断控制器。
200 对于拥有 GICv3 中断控制器并以兼容（v2）模式运行的系统：
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| D | silicon-errata.txt | 74 | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | booting.txt | 195 對於擁有 GICv3 中斷控制器並以 v3 模式運行的系統：
202 - 設備樹（DT）或 ACPI 表必須描述一個 GICv3 中斷控制器。
204 對於擁有 GICv3 中斷控制器並以兼容（v2）模式運行的系統：
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| D | silicon-errata.txt | 78 | Cavium | ThunderX GICv3 | #23154 | CAVIUM_ERRATUM_23154 |
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| /Documentation/virt/kvm/arm/ |
| D | pkvm.rst | 50 - GICv2 is not supported and therefore GICv3 hardware is required in order
51 to expose a virtual GICv3 to the guest.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | socionext,synquacer-exiu.yaml | 15 level-high type GICv3 SPIs.
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| D | arm,gic-v3.yaml | 13 AArch64 SMP cores are often associated with a GICv3, providing Private
196 GICv3 has one or more Interrupt Translation Services (ITS) that are
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| /Documentation/arch/arm64/ |
| D | booting.rst | 223 For systems with a GICv3 interrupt controller to be used in v3 mode:
237 - The DT or ACPI tables must describe a GICv3 interrupt controller.
239 For systems with a GICv3 interrupt controller to be used in
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| D | silicon-errata.rst | 220 | Cavium | ThunderX GICv3 | #23154,38545 | CAVIUM_ERRATUM_23154 |
222 | Cavium | ThunderX GICv3 | #38539 | N/A |
242 | NVIDIA | T241 GICv3/4.x | T241-FABRIC-4 | N/A |
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| D | acpi_object_usage.rst | 244 when using GICv3-ITS and an SMMU); on SBSA Level 0 platforms, it
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| /Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.yaml | 48 For GICv3 and GIC ITS bindings, see:
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| /Documentation/virt/gunyah/ |
| D | index.rst | 70 AArch64 with a GICv3 or GICv4.1
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| /Documentation/virt/hyperv/ |
| D | vpci.rst | 210 arm64 guest VMs because it does not emulate a GICv3 ITS.
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 2806 [KVM,ARM,EARLY] Trap guest accesses to GICv3 group-0
2810 [KVM,ARM,EARLY] Trap guest accesses to GICv3 group-1
2814 [KVM,ARM,EARLY] Trap guest accesses to GICv3 common
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| /Documentation/virt/kvm/ |
| D | api.rst | 3194 to GICv3 ITS in-kernel emulation).
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