Searched full:gmii (Results 1 – 25 of 31) sorted by relevance
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| /Documentation/devicetree/bindings/phy/ |
| D | ti,phy-gmii-sel.yaml | 5 $id: http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#
26 | |Port 1..<--+-->GMII/MII<------->
51 - ti,am3352-phy-gmii-sel
52 - ti,dra7xx-phy-gmii-sel
53 - ti,am43xx-phy-gmii-sel
54 - ti,dm814-phy-gmii-sel
55 - ti,am654-phy-gmii-sel
56 - ti,j7200-cpsw5g-phy-gmii-sel
57 - ti,j721e-cpsw9g-phy-gmii-sel
58 - ti,j784s4-cpsw9g-phy-gmii-sel
[all …]
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| /Documentation/devicetree/bindings/net/ |
| D | xlnx,gmii-to-rgmii.yaml | 4 $id: http://devicetree.org/schemas/net/xlnx,gmii-to-rgmii.yaml#
7 title: Xilinx GMII to RGMII Converter
13 The Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media
24 const: xlnx,gmii-to-rgmii-1.0
55 compatible = "xlnx,gmii-to-rgmii-1.0";
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| D | socfpga-dwmac.txt | 32 - compatible : Should be altr,gmii-to-sgmii-2.0
38 compatible = "altr,gmii-to-sgmii-2.0";
56 altr,gmii-to-sgmii-converter = <&gmii_to_sgmii_converter>;
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| D | cpsw-phy-sel.txt | 21 reg-names = "gmii-sel";
28 reg-names = "gmii-sel";
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| D | microchip,lan966x-switch.yaml | 98 - gmii
158 phy-mode = "gmii";
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| D | qca,ar71xx.yaml | 97 phy-mode = "gmii";
128 phy-mode = "gmii";
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| D | snps,dwc-qos-ethernet.txt | 29 In some configurations (e.g. GMII/RGMII), this clock also drives the PHY TX
34 In some configurations (e.g. GMII/RGMII), this clock is derived from the
146 phy-mode = "gmii";
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| D | ti,cpsw-switch.yaml | 16 gigabit media independent interface (GMII),reduced gigabit media
104 description: phandle on phy-gmii-sel PHY
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| D | ti,dp83867.yaml | 25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
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| D | cpsw.txt | 48 - phys : phandle on phy-gmii-sel PHY (see phy/ti-phy-gmii-sel.txt)
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| D | brcm,systemport.yaml | 79 phy-mode = "gmii";
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| D | xlnx,axi-ethernet.yaml | 12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
61 - gmii
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| D | engleder,tsnep.yaml | 55 - gmii
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| D | renesas,ethertsn.yaml | 14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
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| D | marvell,pp2.yaml | 106 - gmii
226 phy-mode = "gmii";
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| D | ti,dp83869.yaml | 21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
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| D | altr,tse.yaml | 154 phy-mode = "gmii";
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| /Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| D | ucc.txt | 50 i.e., "mii" (default), "rmii", "gmii", "rgmii", "rgmii-id" (Internal
66 phy-connection-type = "gmii";
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| /Documentation/ABI/testing/ |
| D | sysfs-class-net-phydev | 41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | qca,ar9331.yaml | 96 phy-mode = "gmii";
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| D | microchip,ksz.yaml | 69 High Speed Drive Strength. Controls drive strength of GMII / RGMII /
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | ti,j721e-system-controller.yaml | 61 $ref: /schemas/phy/ti,phy-gmii-sel.yaml#
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| /Documentation/devicetree/bindings/net/pcs/ |
| D | snps,dw-xpcs.yaml | 15 the Media Independent Interface (XGMII, USXGMII, XLGMII, GMII, etc)
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | pinctrl_spear.txt | 145 "i2c0", "ssp0", "i2s0", "i2s1", "clcd", "arm_gpio", "smi", "gmii",
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| /Documentation/networking/dsa/ |
| D | bcm_sf2.rst | 19 - several external MII/RevMII/GMII/RGMII interfaces
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