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/Documentation/devicetree/bindings/phy/
Dmicrochip,sparx5-serdes.yaml35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
36 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
37 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
45 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
46 * 3.125 Gbps (2.5GBASE-X/2.5GBASE-KX)
47 * 5 Gbps (QSGMII/USGMII)
48 * 5.15625 Gbps (5GBASE-KR/5G-USXGMII)
49 * 10 Gbps (10G-USGMII)
50 * 10.3125 Gbps (10GBASE-R/10GBASE-KR/USXGMII)
57 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
[all …]
Dapm-xgene-phy.txt1 * APM X-Gene 15Gbps Multi-purpose PHY nodes
3 PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
48 0 = 1-2Gbps
49 1 = 2-4Gbps (1st tuple default)
50 2 = 4-8Gbps
51 3 = 8-15Gbps (2nd tuple default)
52 4 = 2.5-4Gbps
53 5 = 4-5Gbps
54 6 = 5-6Gbps
55 7 = 6-16Gbps (3rd tuple default)
Dmediatek,hdmi-phy.yaml56 TX DRV bias current for < 1.65Gbps
64 TX DRV bias current for >= 1.65Gbps
/Documentation/scsi/
Dbfa.rst16 1657:0013:1657:0014 425 4Gbps dual port FC HBA
17 1657:0013:1657:0014 825 8Gbps PCIe dual port FC HBA
18 1657:0013:103c:1742 HP 82B 8Gbps PCIedual port FC HBA
19 1657:0013:103c:1744 HP 42B 4Gbps dual port FC HBA
20 1657:0017:1657:0014 415 4Gbps single port FC HBA
21 1657:0017:1657:0014 815 8Gbps single port FC HBA
22 1657:0017:103c:1741 HP 41B 4Gbps single port FC HBA
23 1657:0017:103c 1743 HP 81B 8Gbps single port FC HBA
24 1657:0021:103c:1779 804 8Gbps FC HBA for HP Bladesystem c-class
26 1657:0014:1657:0014 1010 10Gbps single port CNA - FCOE
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dmaxim,max96712.yaml21 Each GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
23 MAX96712 can be paired with first-generation 3.12Gbps or 1.5Gbps GMSL1
24 serializers or operate up to 3.12Gbps with GMSL2 serializers in GMSL1 mode.
Dmaxim,max96717.yaml25 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
27 MAX96717F only supports a fixed rate of 3Gbps in the forward direction.
Dmaxim,max96714.yaml23 The GMSL2 serial link operates at a fixed rate of 3Gbps or 6Gbps in the
25 MAX96714F only supports a fixed rate of 3Gbps in the forward direction.
Dsony,imx214.yaml16 maximum throughput of 1.2Gbps/lane.
/Documentation/networking/
Ddctcp.rst19 switches is 20 packets (30KB) at 1Gbps, and 65 packets (~100KB) at 10Gbps,
Dxfrm_device.rst16 computational cost is high: a 10Gbps link can easily be brought down
17 to under 1Gbps, depending on the traffic and link configuration.
Dphy.rst249 data rate of 1Gbps. Embedded in the data stream is a 16-bit control
251 remote end. This does not include "up-clocked" variants such as 2.5Gbps
262 encoding. The underlying data rate is 1Gbps, with the slower speeds of
266 receipt. This does not include "up-clocked" variants such as 2.5Gbps
/Documentation/devicetree/bindings/ata/
Dapm-xgene.txt24 * "sata-phy" for the SATA 6.0Gbps PHY
/Documentation/networking/device_drivers/ethernet/pensando/
Dionic.rst36 ionic 0000:b5:00.0 enp181s0: Link up - 100 Gbps
39 ionic 0000:b6:00.0 enp182s0: Link up - 100 Gbps
/Documentation/devicetree/bindings/usb/
Dmicrochip,usb5744.yaml15 controller, so 5 Gbps SuperSpeed data transfers are not affected by slower
/Documentation/devicetree/bindings/net/
Drenesas,ethertsn.yaml14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
/Documentation/driver-api/
Dinterconnect.rst133 # Set desired BW to 1GBps avg and 2GBps peak.
/Documentation/ABI/testing/
Dsysfs-ata61 eg. 1.5, 3 Gbps etc.
Dsysfs-platform-mellanox-bootctl94 the out-of-band 1Gbps Ethernet port. This MAC address is
/Documentation/devicetree/bindings/net/dsa/
Dnxp,sja1105.yaml106 the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
/Documentation/networking/device_drivers/ethernet/intel/
Dixgbe.rst111 - 82599-based QSFP+ adapters only support 4x10 Gbps connections. 1x40 Gbps
113 4x10 Gbps.
115 The link speed must be configured to either 10 Gbps or 1 Gbps to match the link
De1000e.rst336 duplex mode. Your link partner must match the setting you choose. 1 Gbps speeds
338 manually set devices for 1 Gbps and higher.
/Documentation/arch/x86/
Dresctrl.rst543 where L2 external is 10GBps (hence aggregate L2 external bandwidth is
544 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
545 threads, having 50% bandwidth, each consuming 5GBps' consumes the max L3
546 bandwidth of 100GBps although the percentage value specified is only 50%
556 thread, with 10% bandwidth' can consume upto 10GBps and 40GBps although
/Documentation/networking/device_drivers/ethernet/freescale/
Ddpaa.rst88 tgec ten gigabit Ethernet controller (10 Gbps)
/Documentation/networking/device_drivers/ethernet/altera/
Daltera_tse.rst53 tested for 1Gbps. This support will be added in a future maintenance update.
/Documentation/networking/device_drivers/ethernet/chelsio/
Dcxgb.rst225 eth#: link is up at 10 Gbps, full duplex

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