Searched full:global (Results 1 – 25 of 457) sorted by relevance
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| /Documentation/devicetree/bindings/mailbox/ |
| D | qcom,apcs-kpss-global.yaml | 4 $id: http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#
7 title: Qualcomm APCS global block
10 This binding describes the APCS "global" block found in various Qualcomm
21 - qcom,ipq5018-apcs-apps-global
22 - qcom,ipq5332-apcs-apps-global
23 - qcom,ipq8074-apcs-apps-global
24 - qcom,ipq9574-apcs-apps-global
25 - const: qcom,ipq6018-apcs-apps-global
28 - qcom,qcs404-apcs-apps-global
29 - const: qcom,msm8916-apcs-kpss-global
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| D | mediatek,gce-mailbox.yaml | 7 title: Mediatek Global Command Engine Mailbox
13 The Global Command Engine (GCE) is used to help read/write registers with
46 - description: Global Command Engine clock
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-intel-pmc | 6 The file exposes "Extended Test Mode Register 3" global
9 of the platform is a "global reset". This type of reset
13 Display global reset setting bits for PMC.
15 * bit 31 - global reset is locked
16 * bit 20 - global reset is set
19 a platform "global reset" upon consequent platform reset,
21 The "global reset bit" should be locked on a production
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| D | sysfs-kernel-mm-swap | 13 VMA, and the global swap readahead algorithm will be
15 false, the global swap readahead algorithm will be
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| /Documentation/devicetree/bindings/reset/ |
| D | qcom,pdc-global.yaml | 4 $id: http://devicetree.org/schemas/reset/qcom,pdc-global.yaml#
7 title: Qualcomm PDC Global
13 The bindings describes the reset-controller found on PDC-Global (Power Domain
21 - const: qcom,sc7180-pdc-global
22 - const: qcom,sdm845-pdc-global
26 - const: qcom,sc7280-pdc-global
30 - const: qcom,sdm845-pdc-global
48 compatible = "qcom,sdm845-pdc-global";
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| D | intel,rcu-gw.yaml | 22 intel,global-reset:
23 description: Global reset register offset and bit offset.
45 - intel,global-reset
55 intel,global-reset = <0x10 30>;
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| /Documentation/devicetree/bindings/soc/fsl/ |
| D | guts.txt | 1 * Global Utilities Block
3 The global utilities block controls power management, I/O device
11 global-utilities.
21 - fsl,has-rstcr : Indicates that the global utilities register set
28 - little-endian : Indicates that the global utilities block is little
32 global-utilities@e0000 { /* global utilities block */
38 guts: global-utilities@e0000 {
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| /Documentation/devicetree/bindings/timer/ |
| D | arm,global_timer.yaml | 7 title: ARM Global Timer
13 Cortex-A9 are often associated with a per-core Global timer.
19 - arm,cortex-a5-global-timer
20 - arm,cortex-a9-global-timer
43 compatible = "arm,cortex-a9-global-timer";
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| D | samsung,exynos4210-mct.yaml | 14 global timer and CPU local timers. The global timer is a 64-bit free running
66 interrupts should be specified after the four global timer interrupts
68 0: Global Timer Interrupt 0
69 1: Global Timer Interrupt 1
70 2: Global Timer Interrupt 2
71 3: Global Timer Interrupt 3
81 minItems: 5 # 4 Global + 1 local
82 maxItems: 20 # 4 Global + 16 local
160 // in addition to four global timer interrupts.
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| /Documentation/devicetree/bindings/i3c/ |
| D | aspeed,ast2600-i3c.yaml | 37 aspeed,global-regs:
41 - description: phandle to i3c global register syscon node
42 - description: index of this i3c controller in the global register set
44 A (phandle, controller index) reference to the i3c global register set
52 - aspeed,global-regs
67 aspeed,global-regs = <&i3c_global 0>;
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| /Documentation/admin-guide/perf/ |
| D | hns3-pmu.rst | 64 filter mode supported: global/port/port-tc/func/func-queue/
73 …erf stat -g -e hns3_pmu_sicl_0/bw_ssu_rpu_byte_num,global=1/ -e hns3_pmu_sicl_0/bw_ssu_rpu_time,gl…
75 …$# perf stat -g -e hns3_pmu_sicl_0/config=0x00002,global=1/ -e hns3_pmu_sicl_0/config=0x10002,glob…
81 1. global mode
83 Set the "global" filter option to 1 will enable this mode.
86 $# perf stat -a -e hns3_pmu_sicl_0/config=0x1020F,global=1/ -I 1000
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | sprd,pinctrl.txt | 5 The first block comprises some global control registers, and each
7 to configure for some global common configuration, such as domain
18 global configuration in future. Then we add one "sprd,control" to
19 set these various global control configuration, and we need use
23 bits in one global control register as one pin, thus we should
80 - sprd,control: Control values referring to databook for global control pins.
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| /Documentation/scheduler/ |
| D | sched-ext.rst | 70 local=0 global=3
71 local=5 global=24
72 local=9 global=44
73 local=13 global=56
74 local=17 global=72
125 ``tools/sched_ext/scx_simple.bpf.c`` showing a minimal global FIFO scheduler.
157 * Do a direct dispatch of a task to the global DSQ. This ops.enqueue()
200 priority queue. By default, there is one global FIFO (``SCX_DSQ_GLOBAL``),
211 global DSQ. If that doesn't yield a runnable task either, ``ops.dispatch()``
246 * Immediately dispatch the task to either the global or local DSQ by
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| D | membarrier.rst | 7 MEMBARRIER_CMD_{PRIVATE,GLOBAL}_EXPEDITED - Architecture requirements
18 membarrier_{private,global}_expedited().
39 entry, cf. membarrier_{private,global}_expedited().
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic-timer.txt | 4 - compatible: "fsl,mpic-global-timer"
21 compatible = "fsl,mpic-global-timer";
32 compatible = "fsl,mpic-global-timer";
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| /Documentation/virt/ |
| D | guest-halt-polling.rst | 20 The basic logic as follows: A global value, guest_halt_poll_ns,
43 wakeup event occurs after the global guest_halt_poll_ns.
51 but before global guest_halt_poll_ns.
71 high once achieves global guest_halt_poll_ns value).
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| /Documentation/mm/ |
| D | hugetlbfs_reserv.rst | 34 This is a global (per-hstate) count of reserved huge pages. Reserved
155 the global reservation count resv_huge_pages is adjusted something like the
161 Note that the global lock hugetlb_lock is held when checking and adjusting
164 If there were enough free huge pages and the global count resv_huge_pages
171 If hugetlb_reserve_pages() was successful, the global reservation count and
215 exist and the page must be taken from the global free pool if possible.
226 resv_huge_pages--; /* Decrement the global reservation count */
254 a race is detected, the subpool and global reserve counts are adjusted to
268 to the global reservation count (resv_huge_pages).
278 reserves, or the page is being freed on an error path where a global
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| /Documentation/devicetree/bindings/soc/ti/ |
| D | keystone-navigator-dma.txt | 33 configuration.. Navigator cloud global address needs to be programmed
45 - Global control register region (global).
79 reg-names = "global", "txchan", "rxchan",
89 reg-names = "global", "txchan", "rxchan",
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| /Documentation/core-api/ |
| D | asm-annotations.rst | 18 some functions as *global* in order to be visible outside of their translation
26 intended to denote the beginning of global symbols (be it data or code).
36 25: 0000000000000000 33 FUNC GLOBAL DEFAULT 1 __put_user_1
37 29: 0000000000000030 37 FUNC GLOBAL DEFAULT 1 __put_user_2
38 32: 0000000000000060 36 FUNC GLOBAL DEFAULT 1 __put_user_4
39 35: 0000000000000090 37 FUNC GLOBAL DEFAULT 1 __put_user_8
59 * global/local symbol
111 conventions -- global and local. Like in C, they both align the functions to
163 to C labels, except they can be made global. An example of use::
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| /Documentation/gpu/amdgpu/display/ |
| D | dcn-overview.rst | 24 multiple planes, using global or per-pixel alpha.
67 2. Global sync signals (green): It is a set of synchronization signals composed
73 the Global Sync deserves an extra level of detail described in the next
186 Global Sync
197 These atomic register updates are driven by global sync signals in DCN. In
199 signals page flip and vblank events it is helpful to understand how global sync
202 Global sync consists of three signals, VSTARTUP, VUPDATE, and VREADY. These are
206 The global sync signals always happen during VBlank, are independent from the
218 The below picture illustrates the global sync signals:
225 The following picture shows how global sync allows for a mailbox style of
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| /Documentation/kernel-hacking/ |
| D | false-sharing.rst | 54 * A global datum accessed (shared) by many CPUs
76 * global data being put together in one cache line. Some kernel
77 subsystems have many global parameters of small size (4 bytes),
128 pahole's decoding to locate the exact data members. For global
146 * Separate hot global data in its own dedicated cache line, even if it
159 Like for some global variable, use compare(read)-then-write instead
173 * Turn hot global data to 'per-cpu data + global data' when possible,
175 global data, to reduce or postpone the 'write' to that global data.
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,gcc.yaml | 7 title: Qualcomm Global Clock & Reset Controller Common Properties
14 Common bindings for Qualcomm global clock control module providing the
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| /Documentation/leds/ |
| D | leds-class-multicolor.rst | 43 intensity setting divided by the global max_brightness setting multiplied by
69 global 'brightness' control. Assuming a max_brightness of 255 the user
71 128 to the global brightness file then the values written to each LED will be
82 Reading the global brightness file will return the current brightness value of
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| /Documentation/arch/powerpc/ |
| D | dscr.rst | 37 NOTE: Please note here that the system wide global DSCR value never
42 - Global DSCR default: /sys/devices/system/cpu/dscr_default
45 Changing the global DSCR default in the sysfs will change all the CPU
52 the same thing as above but unlike the global one above, it just changes
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| /Documentation/virt/kvm/ |
| D | halt-polling.rst | 51 the global max polling interval (see module params below), or the total block
52 time was greater than the global max polling interval.
55 the global max polling interval then the polling interval can be increased in
62 In the event that the total block time was greater than the global max polling
63 interval then the host will never poll for long enough (limited by the global
82 The kvm module has 4 tunable module parameters to adjust the global max polling
91 |halt_poll_ns | The global max polling | KVM_HALT_POLL_NS_DEFAULT|
142 global max polling interval (halt_poll_ns) then the host will always poll for the
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