Searched full:hart (Results 1 – 20 of 20) sorted by relevance
| /Documentation/devicetree/bindings/iio/addac/ |
| D | adi,ad74115.yaml | 70 10 - Current output with HART
71 11 - Current input, externally-powered, with HART
72 12 - Current input, loop-powered, with HART
188 adi,dac-hart-slew:
190 description: Whether to use a HART-compatible slew rate.
268 3 - Control HART CD
269 4 - Monitor HART CD
270 5 - Monitor HART EOM status
282 3 - Control HART RXD
283 4 - Monitor HART RXD
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| D | adi,ad74413r.yaml | 20 The AD74413R differentiates itself from the AD74412R by being HART-compatible.
81 HART functions are not supported on AD74412R.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | riscv,imsics.yaml | 17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file
33 privilege level (machine or supervisor) encodes group index, HART index,
36 XLEN-1 > (HART Index MSB) 12 0
39 |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 |
76 HART) as parent.
101 riscv,hart-index-bits:
105 Number of HART index bits in the MSI target address. When not
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| D | riscv,cpu-intc.yaml | 7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
11 each CPU core (HART in RISC-V terminology) and can be read or written by
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
14 before it interrupts that hart.
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| D | sifive,plic-1.0.0.yaml | 14 external interrupts in the system to all hart contexts in the system, via
15 the external interrupt source in each hart.
17 A hart context is a privilege mode in a hardware execution thread. For example,
19 privilege modes per hart; machine mode and supervisor mode.
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| D | riscv,aplic.yaml | 47 node, which has a CPU node (i.e. RISC-V HART) as parent.
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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 18 hart: A hardware execution context, which contains all the state
62 Identifies that the hart uses the RISC-V instruction set
63 and identifies the type of the hart.
68 this hart. These values originate from the RISC-V Privileged
81 The hart ID of this CPU node.
114 by this hart (see ./idle-states.yaml).
190 // Example 2: Spike ISA Simulator with 1 Hart
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| D | extensions.yaml | 18 This document defines properties that indicate whether a hart supports a
37 supported by the hart. These are documented in the RISC-V
56 The base ISA implemented by this hart, as described by the 20191213
65 description: Extensions supported by the hart.
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| /Documentation/arch/riscv/ |
| D | cmodx.rst | 14 applications. At any point the scheduler may migrate a task onto a new hart. If
16 storage with fence.i, the icache on the new hart will no longer be clean. This
17 is due to the behavior of fence.i only affecting the hart that it is called on.
18 Thus, the hart that the task has been migrated to may not have synchronized
29 when the memory map being used by a hart changes. If the prctl() context caused
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| D | uabi.rst | 45 "isa" and "hart isa" lines in /proc/cpuinfo
50 "hart isa" line, in contrast, describes the set of extensions recognized by the
51 kernel on the particular hart being described, even if those extensions may not
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| D | boot.rst | 68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart
72 - ``Ordered booting``: the firmware releases only one hart that will execute the
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| /Documentation/devicetree/bindings/timer/ |
| D | sifive,clint.yaml | 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-wmi | 76 Contact: Darren Hart (VMware) <dvhart@infradead.org>
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| /Documentation/devicetree/bindings/cpu/ |
| D | idle-states.yaml | 57 RISC-V SBI v0.3 (or higher) [7] hart state management extension provides a
58 standard mechanism for OS to request HART state transitions.
60 The platform specific suspend (or idle) states of a hart can be either
62 preserve HART registers and CSR values for all privilege modes whereas
63 a non-retentive suspend state will not preserve HART registers and CSR
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| /Documentation/devicetree/bindings/iio/temperature/ |
| D | adi,ltc2983.yaml | 308 26 - Thermistor Custom Steinhart-Hart
356 Steinhart-Hart coefficients in raw format, used for digitizing
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| /Documentation/timers/ |
| D | highres.rst | 64 Timers" was written by J. Stultz, D.V. Hart, & N. Aravamudan.
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| /Documentation/process/ |
| D | embargoed-hardware-issues.rst | 291 Ampere Darren Hart <darren@os.amperecomputing.com>
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| /Documentation/translations/sp_SP/process/ |
| D | embargoed-hardware-issues.rst | 271 Ampere Darren Hart <darren@os.amperecomputing.com>
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| /Documentation/RCU/ |
| D | RTFP.txt | 1132 ,Author="Thomas E. Hart"
1270 ,Author="Thomas E. Hart and Paul E. McKenney and Angela Demke Brown"
1442 ,Author="Thomas E. Hart and Paul E. McKenney and Angela Demke Brown"
1911 ,Author="Thomas E. Hart and Paul E. McKenney and Angela Demke Brown and Jonathan Walpole"
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| /Documentation/admin-guide/media/ |
| D | bttv.rst | 1653 - HART Vision 848 (H-ART Vision 848)
1654 - HART Vision 878 (H-Art Vision 878)
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