Searched full:harts (Results 1 – 9 of 9) sorted by relevance
49 RISC-V ISA extensions recognized by the kernel and implemented on all harts. The52 be present on all harts in the system.
68 - ``RISCV_BOOT_SPINWAIT``: the firmware releases all harts in the kernel, one hart69 wins a lottery and executes the early boot code while the other harts are73 initialization phase and then will start all other harts using the SBI HSM
22 which is same for given privilege level across CPUs (or HARTs).26 IMSIC interrupt files at that privilege level across CPUs (or HARTs).73 This property represents the set of CPUs (or HARTs) for which given
46 RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc114 // Example 1 (APLIC domains directly injecting interrupt to HARTs):
31 present HARTs in the system.
18 in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
24 having four harts.
55 On RISC-V systems, the HARTs (or CPUs) [6] can be put in platform specific