| /Documentation/scsi/ |
| D | scsi-parameters.rst | 19 advansys= [HW,SCSI]
22 aha152x= [HW,SCSI]
25 aha1542= [HW,SCSI]
28 aic7xxx= [HW,SCSI]
31 aic79xx= [HW,SCSI]
34 atascsi= [HW,SCSI]
37 BusLogic= [HW,SCSI]
41 gvp11= [HW,SCSI]
43 ips= [HW,SCSI] Adaptec / IBM ServeRAID controller
46 mac5380= [HW,SCSI]
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| /Documentation/watchdog/ |
| D | mlx-wdt.rst | 13 There are 2 types of HW watchdog implementations.
16 Actual HW timeout can be defined as a power of 2 msec.
22 Actual HW timeout is defined in sec. and it's the same as
31 Type 1 HW watchdog implementation exist in old systems and
32 all new systems have type 2 HW watchdog.
33 Two types of HW implementation have also different register map.
35 Type 3 HW watchdog implementation can exist on all Mellanox systems
54 This mlx-wdt driver supports both HW watchdog implementations.
60 watchdog configuration flags: nowayout and start_at_boot, hw watchdog
65 Access to HW registers is performed through a generic regmap interface.
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| /Documentation/networking/device_drivers/ethernet/huawei/ |
| D | hinic.rst | 35 specific HW details about HW data structure formats.
37 hinic_hwdev - Implement the HW details of the device and include the components
43 HW Interface:
49 Configuration Status Registers Area that describes the HW Registers on the
63 card by AEQs. Also set the addresses of the IO CMDQs in HW.
78 used to set the QPs addresses in HW. The commands completion events are
82 Queue Pairs(QPs) - The HW Receive and Send queues for Receiving and Transmitting
87 HW device:
90 HW device - de/constructs the HW Interface, the MGMT components on the
101 Port Commands - Send commands to the HW device for port management
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| /Documentation/gpu/amdgpu/display/ |
| D | dcn-blocks.rst | 11 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
17 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h
23 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
26 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h
32 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
35 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h
42 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
45 .. kernel-doc:: drivers/gpu/drm/amd/display/dc/inc/hw/opp.h
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-qcom-hw.yaml | 4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-qcom-hw.yaml#
14 CPUFREQ HW is a hardware engine used by some Qualcomm Technologies, Inc. (QTI)
21 - description: v1 of CPUFREQ HW
24 - qcom,qcm2290-cpufreq-hw
25 - qcom,sc7180-cpufreq-hw
26 - qcom,sdm670-cpufreq-hw
27 - qcom,sdm845-cpufreq-hw
28 - qcom,sm6115-cpufreq-hw
29 - qcom,sm6350-cpufreq-hw
30 - qcom,sm8150-cpufreq-hw
[all …]
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| D | cpufreq-mediatek-hw.yaml | 4 $id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek-hw.yaml#
13 CPUFREQ HW is a hardware engine used by MediaTek SoCs to
19 const: mediatek,cpufreq-hw
25 Addresses and sizes for the memory of the HW bases in
65 compatible = "mediatek,cpufreq-hw";
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| D | imx-cpufreq-dt.txt | 6 the opp-supported-hw values for each OPP to check if the OPP is allowed.
12 - opp-supported-hw: Two bitmaps indicating:
28 opp-supported-hw = <0xf>, <0x3>;
35 opp-supported-hw = <0xe>, <0x7>;
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| /Documentation/driver-api/iio/ |
| D | hw-consumer.rst | 2 HW consumer
6 The Industrial I/O HW consumer offers a way to bond these IIO devices without
8 :file:`drivers/iio/buffer/hw-consumer.c`
18 HW consumer setup
22 A typical IIO HW consumer setup looks like this::
48 .. kernel-doc:: drivers/iio/buffer/industrialio-hw-consumer.c
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| /Documentation/networking/dsa/ |
| D | lan9303.rst | 21 interfaces (which is the default state of a DSA device). Due to HW limitations,
22 no HW MAC learning takes place in this mode.
24 When both user ports are joined to the same bridge, the normal HW MAC learning
25 is enabled. This means that unicast traffic is forwarded in HW. Broadcast and
26 multicast is flooded in HW. STP is also supported in this mode. The driver
37 - The HW does not support VLAN-specific fdb entries
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| /Documentation/driver-api/ |
| D | clk.rst | 51 struct clk_hw *hw;
70 int (*prepare)(struct clk_hw *hw);
71 void (*unprepare)(struct clk_hw *hw);
72 int (*is_prepared)(struct clk_hw *hw);
73 void (*unprepare_unused)(struct clk_hw *hw);
74 int (*enable)(struct clk_hw *hw);
75 void (*disable)(struct clk_hw *hw);
76 int (*is_enabled)(struct clk_hw *hw);
77 void (*disable_unused)(struct clk_hw *hw);
78 unsigned long (*recalc_rate)(struct clk_hw *hw,
[all …]
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| /Documentation/netlink/specs/ |
| D | netdev.yaml | 32 name: hw-offload
34 This feature informs if netdev supports XDP hw offloading.
52 Device is capable of exposing receive HW timestamp via bpf_xdp_metadata_rx_timestamp().
68 HW timestamping egress packets is supported by the driver.
72 L3 checksum HW offload is supported by the driver.
347 name: rx-hw-drops
355 name: rx-hw-drop-overruns
379 name: rx-hw-gro-packets
382 Counts only packets coalesced with the HW-GRO netdevice feature,
386 name: rx-hw-gro-bytes
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-etb10 | 27 2. The value is read directly from HW register RDP, 0x004.
34 is read directly from HW register STS, 0x00C.
42 interface. The value is read directly from HW register RRP,
52 from HW register RWP, 0x018.
59 read directly from HW register TRG, 0x01C.
66 is read directly from HW register CTL, 0x020.
73 register. The value is read directly from HW register FFSR,
81 register. The value is read directly from HW register FFCR,
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| D | sysfs-bus-coresight-devices-tmc | 15 The value is read directly from HW register RSZ, 0x004.
22 is read directly from HW register STS, 0x00C.
30 interface. The value is read directly from HW register RRP,
40 from HW register RWP, 0x018.
47 read directly from HW register TRG, 0x01C.
54 is read directly from HW register CTL, 0x020.
61 register. The value is read directly from HW register FFSR,
69 register. The value is read directly from HW register FFCR,
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| D | sysfs-bus-coresight-devices-etm4x | 337 The value it taken directly from the HW.
344 (0x310). The value is taken directly from the HW.
351 (0x314). The value is taken directly from the HW.
358 (0xFB4). The value is taken directly from the HW.
365 (0xFB8). The value is taken directly from the HW.
372 (0xFC8). The value is taken directly from the HW.
380 from the HW.
387 (0xFCC). The value is taken directly from the HW.
394 (0xFE0). The value is taken directly from the HW.
401 (0xFE4). The value is taken directly from the HW.
[all …]
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| /Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 47 - hw-caps-read-idle-ctrl: Have this property if the controller
50 - hw-caps-dll-calib-ctrl: Have this property if the controller
53 - hw-caps-ll-interface : Have this property if the controller
56 - hw-caps-temp-alert : Have this property if the controller
67 hw-caps-read-idle-ctrl;
68 hw-caps-ll-interface;
69 hw-caps-temp-alert;
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| /Documentation/leds/ |
| D | leds-class.rst | 180 With hw control we refer to the LED driven by hardware.
182 LED driver must define the following value to support hw control:
185 unique trigger name supported by the LED in hw control
188 LED driver must implement the following API to support hw control:
191 be parsed and activate hw control on the LED.
204 activate hw control. LED driver will use the provided
209 Set LED_OFF via the brightness_set to deactivate hw control.
215 get active modes from a LED already in hw control, parse
227 hw control. A trigger might use this to match the
230 events and correctly enable hw control.
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| /Documentation/devicetree/bindings/regulator/ |
| D | rohm,bd71815-regulator.yaml | 56 PMIC "RUN" state voltage in uV when PMIC HW states are used. See
76 PMIC "SUSPEND" state voltage in uV when PMIC HW states are used. See
85 PMIC "LPSR" state voltage in uV when PMIC HW states are used. See
94 # (LPSR/SUSPEND). The voltage is automatically changed when HW
96 # buck voltages to not be toggled by HW state. Enable status may still
97 # be toggled by state changes depending on HW default settings.
106 # for each of the HW states (RUN/SNVS/SUSPEND/LPSR). HW defaults can
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| /Documentation/devicetree/bindings/opp/ |
| D | operating-points-v2-ti-cpu.yaml | 48 opp-supported-hw: true
54 - opp-supported-hw
71 opp-supported-hw = <0x06 0x0020>;
78 opp-supported-hw = <0x01 0xFFFF>;
84 opp-supported-hw = <0x06 0x0040>;
90 opp-supported-hw = <0x04 0x0200>;
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| D | opp-v2-kryo-cpu.yaml | 23 the OPP framework with required information (existing HW bitmap).
54 opp-supported-hw:
56 A single 32 bit bitmap value, representing compatible HW.
99 - opp-supported-hw
216 opp-supported-hw = <0x7>;
223 opp-supported-hw = <0x5>;
230 opp-supported-hw = <0x1>;
244 opp-supported-hw = <0x7>;
251 opp-supported-hw = <0x6>;
258 opp-supported-hw = <0x4>;
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| /Documentation/devicetree/bindings/thermal/ |
| D | rockchip-thermal.yaml | 60 rockchip,hw-tshut-temp:
64 rockchip,hw-tshut-mode:
69 rockchip,hw-tshut-polarity:
98 rockchip,hw-tshut-temp = <95000>;
99 rockchip,hw-tshut-mode = <0>;
100 rockchip,hw-tshut-polarity = <0>;
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | interface.txt | 17 "ti,omap3-hsotgusb-interface-clock" - interface clock with USB specific HW
19 "ti,omap3-dss-interface-clock" - interface clock with DSS specific HW handling
20 "ti,omap3-ssi-interface-clock" - interface clock with SSI specific HW handling
21 "ti,am35xx-interface-clock" - interface clock with AM35xx specific HW handling
22 "ti,omap2430-interface-clock" - interface clock with OMAP2430 specific HW
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| /Documentation/networking/ |
| D | ieee802154.rst | 136 .. c:function:: void ieee802154_rx_irqsafe(struct ieee802154_hw *hw, struct sk_buff *skb, u8 lqi)
141 .. c:function:: void ieee802154_xmit_complete(struct ieee802154_hw *hw, struct sk_buff *skb, bool i…
151 int (*start)(struct ieee802154_hw *hw);
152 void (*stop)(struct ieee802154_hw *hw);
154 int (*xmit_async)(struct ieee802154_hw *hw, struct sk_buff *skb);
155 int (*ed)(struct ieee802154_hw *hw, u8 *level);
156 int (*set_channel)(struct ieee802154_hw *hw, u8 page, u8 channel);
160 .. c:function:: int start(struct ieee802154_hw *hw)
164 .. c:function:: void stop(struct ieee802154_hw *hw)
168 .. c:function:: int xmit_async(struct ieee802154_hw *hw, struct sk_buff *skb)
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| /Documentation/sound/cards/ |
| D | audiophile-usb.rst | 127 * hw:1,0 is Ao in playback and Di in capture
128 * hw:1,1 is Do in playback and Ai in capture
129 * hw:1,2 is Do in AC3/DTS passthrough mode
135 One exception is the hw:1,2 port which was reported to be Little Endian
137 This has been fixed in kernel 2.6.23 and above and now the hw:1,2 interface
144 % aplay -D hw:1,0 -c2 -t raw -r48000 -fS24_3BE test.raw
148 % arecord -D hw:1,1 -c2 -t raw -r48000 -fS24_3BE test.raw
152 % aplay -D hw:1,1 -c2 -t raw -r48000 -fS16_BE test.raw
156 % aplay -D hw:1,2 --channels=6 ac3_S16_BE_encoded_file.raw
199 - hw:1,0 is not available in capture mode
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| /Documentation/trace/coresight/ |
| D | coresight-tpda.rst | 49 other trace event hw components in the same HW block with tpdm, tpdm
50 and these hw components will connect to the coresight funnel. When
51 there is only tpdm trace hw in the HW block, tpdm will connect to
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| /Documentation/devicetree/bindings/reset/ |
| D | reset.txt | 21 in hardware for a reset signal to affect multiple logically separate HW blocks
23 the DT node of each affected HW block, since if activated, an unrelated block
26 children of the bus are affected by the reset signal, or an individual HW
28 appropriate software access to the reset signals in order to manage the HW,
29 rather than to slavishly enumerate the reset signal that affects each HW
|