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Searched full:hypertransport (Results 1 – 7 of 7) sorted by relevance

/Documentation/devicetree/bindings/interrupt-controller/
Dloongson,pch-msi.yaml14 transforming interrupts from PCIe MSI into HyperTransport vectorized
26 u32 value of the base of parent HyperTransport vector allocated
34 u32 value of the number of parent HyperTransport vectors allocated
Dloongson,htpic.yaml7 title: Loongson-3 HyperTransport Interrupt Controller
17 interrupts from PCH PIC connected on HyperTransport bus.
Dloongson,pch-pic.yaml14 transforming interrupts from on-chip devices into HyperTransport vectorized
26 u32 value of the base of parent HyperTransport vector allocated
Dloongson,htvec.yaml7 title: Loongson-3 HyperTransport Interrupt Vector Controller
/Documentation/networking/device_drivers/ethernet/chelsio/
Dcxgb.rst304 on an AMD Opteron system with HyperTransport PCI-X Tunnel chipset.
306 If your AMD Opteron system uses the AMD-8131 HyperTransport PCI-X Tunnel
/Documentation/arch/loongarch/
Dirq-chip-model.rst187 - HTVECINTC is "HyperTransport Interrupts" described in Section 14.3 of
/Documentation/PCI/
Dmsi-howto.rst243 PCI configuration space (especially the Hypertransport chipsets such