| /Documentation/fb/ |
| D | viafb.modes | 10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
14 # Scan Frequency 31.469 kHz 59.94 Hz
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
39 # Scan Frequency 37.500 kHz 75.00 Hz
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
60 # Scan Frequency 43.269 kHz 85.00 Hz
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
[all …]
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| D | viafb.rst | 21 640x480(60, 75, 85, 100, 120 Hz), 720x480(60 Hz),
22 720x576(60 Hz), 800x600(60, 75, 85, 100, 120 Hz),
23 848x480(60 Hz), 856x480(60 Hz), 1024x512(60 Hz),
24 1024x768(60, 75, 85, 100 Hz), 1152x864(75 Hz),
25 1280x768(60 Hz), 1280x960(60 Hz), 1280x1024(60, 75, 85 Hz),
26 1440x1050(60 Hz), 1600x1200(60, 75 Hz), 1280x720(60 Hz),
27 1920x1080(60 Hz), 1400x1050(60 Hz), 800x480(60 Hz)
|
| /Documentation/ABI/testing/ |
| D | sysfs-bus-iio-adc-ad4130 | 8 1st conversion time. No natural 50/60Hz rejection.
16 * "sinc3+rej60" - Sinc3 + 60Hz rejection. At a sampling
17 frequency of 50Hz, achieves simultaneous 50Hz and 60Hz
22 216.19Hz.
25 50Hz, 58dB rejection @ 60Hz.
28 50Hz, 70dB rejection @ 60Hz.
31 50Hz, 103dB rejection @ 60Hz.
34 50Hz, 109dB rejection @ 60Hz.
|
| /Documentation/devicetree/bindings/interconnect/ |
| D | mediatek,cci.yaml | 79 opp-hz = /bits/ 64 <273000000>;
83 opp-hz = /bits/ 64 <338000000>;
87 opp-hz = /bits/ 64 <403000000>;
91 opp-hz = /bits/ 64 <463000000>;
95 opp-hz = /bits/ 64 <546000000>;
99 opp-hz = /bits/ 64 <624000000>;
103 opp-hz = /bits/ 64 <689000000>;
107 opp-hz = /bits/ 64 <767000000>;
111 opp-hz = /bits/ 64 <845000000>;
115 opp-hz = /bits/ 64 <871000000>;
[all …]
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| /Documentation/leds/ |
| D | leds-mlxcpld.rst | 59 - [0,1,1,0] = Red blink 3Hz
60 - [1,1,1,0] = Green blink 3Hz
61 - [0,1,1,1] = Red blink 6Hz
62 - [1,1,1,1] = Green blink 6Hz
104 - [0,1,1,0] = Red blink 3Hz
105 - [1,1,1,0] = Green blink 3Hz
106 - [0,1,1,1] = Red blink 6Hz
107 - [1,1,1,1] = Green blink 6Hz
114 - [1,1,1,0] = Blue blink 3Hz
115 - [1,1,1,1] = Blue blink 6Hz
[all …]
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| /Documentation/devicetree/bindings/cpufreq/ |
| D | cpufreq-mediatek.txt | 41 opp-hz = /bits/ 64 <598000000>;
46 opp-hz = /bits/ 64 <747500000>;
51 opp-hz = /bits/ 64 <1040000000>;
56 opp-hz = /bits/ 64 <1196000000>;
61 opp-hz = /bits/ 64 <1300000000>;
101 opp-hz = /bits/ 64 <507000000>;
106 opp-hz = /bits/ 64 <702000000>;
111 opp-hz = /bits/ 64 <1001000000>;
116 opp-hz = /bits/ 64 <1105000000>;
121 opp-hz = /bits/ 64 <1183000000>;
[all …]
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| /Documentation/hwmon/ |
| D | adt7470.rst | 78 * 11.0 Hz
79 * 14.7 Hz
80 * 22.1 Hz
81 * 29.4 Hz
82 * 35.3 Hz
83 * 44.1 Hz
84 * 58.8 Hz
85 * 88.2 Hz
|
| /Documentation/devicetree/bindings/ufs/ |
| D | ufs-common.yaml | 18 freq-table-hz:
21 - description: Minimum frequency for given clock in Hz
22 - description: Maximum frequency for given clock in Hz
27 Array of <min max> operating frequencies in Hz stored in the same order
34 Preferred over freq-table-hz.
93 freq-table-hz: [ clocks ]
102 - freq-table-hz
111 freq-table-hz: false
|
| /Documentation/input/devices/ |
| D | cma3000_d0x.rst | 26 axis and supports 400, 100, 40 Hz sample frequency.
112 1: 100 Hz Measurement mode
113 2: 400 Hz Measurement mode
114 3: 40 Hz Measurement mode
116 5: 100 Hz Free fall mode
117 6: 40 Hz Free fall mode
133 (X & 0x0F) * 2.5 ms (FFTMR 400 Hz)
134 (X & 0x0F) * 10 ms (FFTMR 100 Hz)
|
| /Documentation/devicetree/bindings/opp/ |
| D | allwinner,sun50i-h6-operating-points.yaml | 48 opp-hz: true
61 - opp-hz
76 opp-hz = /bits/ 64 <480000000>;
85 opp-hz = /bits/ 64 <1080000000>;
94 opp-hz = /bits/ 64 <1488000000>;
110 opp-hz = /bits/ 64 <480000000>;
118 opp-hz = /bits/ 64 <792000000>;
127 opp-hz = /bits/ 64 <1512000000>;
|
| D | operating-points-v2-ti-cpu.yaml | 46 opp-hz: true
53 - opp-hz
69 opp-hz = /bits/ 64 <300000000>;
76 opp-hz = /bits/ 64 <500000000>;
82 opp-hz = /bits/ 64 <600000000>;
88 opp-hz = /bits/ 64 <1000000000>;
|
| D | opp-v2.yaml | 59 opp-hz = /bits/ 64 <1000000000>;
66 opp-hz = /bits/ 64 <1100000000>;
72 opp-hz = /bits/ 64 <1200000000>;
142 opp-hz = /bits/ 64 <1000000000>;
149 opp-hz = /bits/ 64 <1100000000>;
155 opp-hz = /bits/ 64 <1200000000>;
222 opp-hz = /bits/ 64 <1000000000>;
229 opp-hz = /bits/ 64 <1100000000>;
235 opp-hz = /bits/ 64 <1200000000>;
248 opp-hz = /bits/ 64 <1300000000>;
[all …]
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | atmel,sama5d2-adc.yaml | 34 atmel,min-sample-rate-hz:
37 atmel,max-sample-rate-hz:
71 - atmel,min-sample-rate-hz
72 - atmel,max-sample-rate-hz
89 atmel,min-sample-rate-hz = <200000>;
90 atmel,max-sample-rate-hz = <20000000>;
|
| D | adi,ad7192.yaml | 75 adi,rejection-60-Hz-enable:
77 This bit enables a notch at 60 Hz when the first notch of the sinc
78 filter is at 50 Hz. When REJ60 is set, a filter notch is placed at
79 60 Hz when the sinc filter first notch is at 50 Hz. This allows
80 simultaneous 50 Hz/ 60 Hz rejection.
204 adi,rejection-60-Hz-enable;
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| /Documentation/devicetree/bindings/hwmon/ |
| D | adt7475.yaml | 61 - 90909091 (11 Hz)
62 - 71428571 (14 Hz)
63 - 45454545 (22 Hz)
64 - 34482759 (29 Hz)
65 - 28571429 (35 Hz)
66 - 22727273 (44 Hz)
67 - 17241379 (58 Hz)
68 - 11363636 (88 Hz)
|
| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 116 Defines the PHY dll bypass frequency in MHz (Mega Hz). When DDR frequency
131 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
179 frequency in Hz. When DDR frequency is less then ddr3_odt_dis_freq, the
226 frequency in Hz. When the DDR frequency is less then ddr3_odt_dis_freq,
316 rockchip,pd-idle-dis-freq-hz:
318 Defines the power-down idle disable frequency in Hz. When the DDR
322 rockchip,sr-idle-dis-freq-hz:
324 Defines the self-refresh idle disable frequency in Hz. When the DDR
328 rockchip,sr-mc-gate-idle-dis-freq-hz:
331 frequency in Hz. When the DDR frequency is greater than
[all …]
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| /Documentation/scheduler/ |
| D | sched-nice-design.rst | 14 units were driven by the HZ tick, so the smallest timeslice was 1/HZ.
44 HZ=1000 it caused 1 jiffy to be 1 msec, which meant 0.1% CPU usage which
51 So for HZ=1000 we changed nice +19 to 5msecs, because that felt like the
53 But the fundamental HZ-sensitive property for nice+19 still remained,
59 within the constraints of HZ and jiffies and their nasty design level
91 enough), the scheduler was decoupled from 'time slice' and HZ concepts
94 support: with the new scheduler nice +19 tasks get a HZ-independent
|
| /Documentation/devicetree/bindings/input/ |
| D | pwm-beeper.yaml | 22 beeper-hz:
23 description: bell frequency in Hz
40 beeper-hz = <1000>;
|
| /Documentation/devicetree/bindings/gpu/ |
| D | arm,mali-midgard.yaml | 173 opp-hz = /bits/ 64 <533000000>;
177 opp-hz = /bits/ 64 <450000000>;
181 opp-hz = /bits/ 64 <400000000>;
185 opp-hz = /bits/ 64 <350000000>;
189 opp-hz = /bits/ 64 <266000000>;
193 opp-hz = /bits/ 64 <160000000>;
197 opp-hz = /bits/ 64 <100000000>;
|
| /Documentation/gpu/ |
| D | panfrost.rst | 27 drm-maxfreq-fragment: 799999987 Hz
28 drm-curfreq-fragment: 799999987 Hz
31 drm-maxfreq-vertex-tiler: 799999987 Hz
32 drm-curfreq-vertex-tiler: 799999987 Hz
|
| /Documentation/devicetree/bindings/display/msm/ |
| D | qcom,x1e80100-mdss.yaml | 150 opp-hz = /bits/ 64 <200000000>;
155 opp-hz = /bits/ 64 <325000000>;
160 opp-hz = /bits/ 64 <375000000>;
165 opp-hz = /bits/ 64 <514000000>;
230 opp-hz = /bits/ 64 <160000000>;
235 opp-hz = /bits/ 64 <270000000>;
240 opp-hz = /bits/ 64 <540000000>;
245 opp-hz = /bits/ 64 <810000000>;
|
| D | qcom,sm7150-mdss.yaml | 189 opp-hz = /bits/ 64 <19200000>;
194 opp-hz = /bits/ 64 <200000000>;
199 opp-hz = /bits/ 64 <300000000>;
204 opp-hz = /bits/ 64 <344000000>;
209 opp-hz = /bits/ 64 <430000000>;
273 opp-hz = /bits/ 64 <180000000>;
278 opp-hz = /bits/ 64 <275000000>;
283 opp-hz = /bits/ 64 <358000000>;
437 opp-hz = /bits/ 64 <160000000>;
442 opp-hz = /bits/ 64 <270000000>;
[all …]
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| D | qcom,sm7150-dpu.yaml | 118 opp-hz = /bits/ 64 <19200000>;
123 opp-hz = /bits/ 64 <200000000>;
128 opp-hz = /bits/ 64 <300000000>;
133 opp-hz = /bits/ 64 <344000000>;
138 opp-hz = /bits/ 64 <430000000>;
|
| D | qcom,sm8450-dpu.yaml | 114 opp-hz = /bits/ 64 <172000000>;
119 opp-hz = /bits/ 64 <200000000>;
124 opp-hz = /bits/ 64 <325000000>;
129 opp-hz = /bits/ 64 <375000000>;
134 opp-hz = /bits/ 64 <500000000>;
|
| /Documentation/devicetree/bindings/sound/ |
| D | cs42l56.txt | 47 0 = 1.8Hz
48 1 = 119Hz
49 2 = 236Hz
50 3 = 464Hz
|