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7 title: RISC-V Incoming MSI Controller (IMSIC)14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V17 The IMSIC is a per-CPU (or per-HART) device with separate interrupt file19 a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO20 space to receive MSIs from devices. Each IMSIC interrupt file supports a24 The device tree of a RISC-V platform will have one IMSIC device tree node26 IMSIC interrupt files at that privilege level across CPUs (or HARTs).28 The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform29 follows a particular scheme defined by the RISC-V AIA specification. A IMSIC30 group is a set of IMSIC interrupt files co-located in MMIO space and we can[all …]
52 message signaled interrupt controller (IMSIC). If both "msi-parent" and