Searched full:ipu (Results 1 – 17 of 17) sorted by relevance
| /Documentation/devicetree/bindings/display/ |
| D | ingenic,ipu.yaml | 4 $id: http://devicetree.org/schemas/display/ingenic,ipu.yaml#
7 title: Ingenic SoCs Image Processing Unit (IPU)
16 - ingenic,jz4725b-ipu
17 - ingenic,jz4760-ipu
19 - const: ingenic,jz4770-ipu
20 - const: ingenic,jz4760-ipu
32 const: ipu
49 ipu@13080000 {
50 compatible = "ingenic,jz4770-ipu", "ingenic,jz4760-ipu";
57 clock-names = "ipu";
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| D | ingenic,lcd.yaml | 56 description: Link to the Image Processing Unit (IPU).
57 (See ingenic,ipu.yaml).
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,omap-remoteproc.yaml | 21 The OMAP SoCs usually have a DSP processor sub-system and/or an IPU processor
23 C66x or C67x family of DSP cores as the main execution unit. The IPU processor
45 - ti,omap4-ipu
46 - ti,omap5-ipu
47 - ti,dra7-ipu
108 'reg-names'. These are mandatory for all DSP and IPU
193 - ti,omap4-ipu
194 - ti,omap5-ipu
195 - ti,dra7-ipu
258 //Example 2: OMAP5 IPU
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| /Documentation/devicetree/bindings/display/imx/ |
| D | fsl-imx-drm.txt | 5 IPU or other display interface nodes that comprise the graphics subsystem.
10 of IPU devices
24 - compatible: Should be "fsl,<chip>-ipu" where <chip> is one of
35 Additional required properties for fsl,imx6qp-ipu:
36 - fsl,prg: phandle to prg node associated with this IPU instance
45 ipu: ipu@18000000 {
48 compatible = "fsl,imx53-ipu";
127 Port 0 is the input port connected to the IPU display interface,
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| D | ldb.txt | 14 multiplexer in the front to select any of the four IPU display
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| /Documentation/devicetree/bindings/media/ |
| D | imx.txt | 14 sensor interface ports of IPU devices
34 to the i.MX IPU CSIs.
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| /Documentation/userspace-api/media/drivers/ |
| D | imx-uapi.rst | 34 this happens, the IPU triggers a mechanism to re-establish vertical
46 While the reason for this observation isn't known (the IPU dummy
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| /Documentation/admin-guide/media/ |
| D | ipu6-isys.rst | 34 firmware authentication, DMA mapping and IPU-MMU (internal Memory mapping Unit)
86 machine, ov01a10 sensor is connected to IPU ISYS CSI-2 port 2, which can
95 # This example assumes /dev/media0 as the IPU ISYS media device
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| D | imx.rst | 9 The Freescale i.MX5/6 contains an Image Processing Unit (IPU), which
13 For image capture, the IPU contains the following internal subunits:
43 The IPU time-shares the IC task operations. The time-slice granularity
63 In addition to the IPU internal subunits, there are also two units
64 outside the IPU that are also involved in video capture on i.MX:
148 is a "CSI-2 to IPU gasket". The gasket acts as a demultiplexer of the
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| D | imx7.rst | 10 Unit (IPU); because of that the capabilities to perform operations or
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| /Documentation/devicetree/bindings/reset/ |
| D | fsl,imx-src.yaml | 14 IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
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| /Documentation/devicetree/bindings/dma/ |
| D | fsl,imx-sdma.yaml | 88 - IPU Memory: 19
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| /Documentation/driver-api/media/drivers/ |
| D | ipu6.rst | 135 inter-processor communication mechanism between the IPU scalar processors and
138 memory region via the IPU MMU. The Syscom queues are FIFO fixed depth queues
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| /Documentation/ABI/testing/ |
| D | sysfs-fs-f2fs | 54 0x00 DISABLE disable IPU(=default option in LFS mode)
61 flash storages. IPU will be triggered only if the
64 0x20 ASYNC do IPU given by asynchronous write requests
65 0x40 NOCACHE disable IPU bio cache
66 0x80 HONOR_OPU_WRITE use OPU write prior to IPU write if inode has
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| /Documentation/admin-guide/hw-vuln/ |
| D | processor_mmio_stale_data.rst | 250 Intel processors or platforms, utilizing the Intel Platform Update (IPU)
254 longer provide Servicing, such as through IPU or other similar update
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| D | indirect-target-selection.rst | 22 executed prior to the IBPB. This is fixed by the IPU 2025.1 microcode, which
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| /Documentation/devicetree/bindings/mailbox/ |
| D | ti,omap-mailbox.yaml | 253 mbox_ipu: mbox-ipu {
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