Searched full:ips (Results 1 – 25 of 37) sorted by relevance
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| /Documentation/gpu/amdgpu/ |
| D | driver-core.rst | 9 "IPs" (Intellectual Property blocks). Each IP encapsulates certain
10 functionality. IPs are versioned and can also be mixed and matched.
11 E.g., you might have two different ASICs that both have System DMA (SDMA) 5.x IPs.
12 The driver is arranged by IPs. There are driver components to handle
14 of smaller IPs that don't really need much if any driver interaction.
17 the SoC itself rather than specific IPs. E.g., things like GPU resets
29 With respect to the GPU, we have the following major IPs:
34 have dedicated memory hubs for specific IPs or groups of IPs. We
37 different IPs on the GPU get the memory (VRAM or system memory).
42 This is the interrupt controller on the GPU. All of the IPs feed
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| /Documentation/devicetree/bindings/clock/ |
| D | samsung,exynos5433-clock.yaml | 35 # UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS IPs
37 # CMU_PERIS which generates clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC IPs
39 # CMU_FSYS which generates clocks for USB/UFS/SDMMC/TSI/PDMA IPs
42 # CMU_DISP which generates clocks for Display (DECON/HDMI/DSIM/MIXER) IPs
55 # JPEG IPs
59 # CMU_ISP which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs
62 # MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs
65 # Cortex-A5/MIPI_CSIS2/FIMC-LITE_C/FIMC-FD IPs
68 # SlimSSS IPs
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| D | keystone-pll.txt | 2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL
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| /Documentation/devicetree/bindings/hwmon/ |
| D | moortec,mr75203.yaml | 15 Such a design will usually consists of several Moortec's embedded analog IPs,
16 and a single Moortec controller (mr75203) to configure and control the IPs.
18 Some of the Moortec's analog hard IPs that can be used in a design:
36 for some of the analog IPs.
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| /Documentation/networking/ |
| D | cdc_mbim.rst | 173 Multiplexed IP sessions (IPS)
275 This mapping implies a few restrictions on multiplexed IPS and DSS
278 - no IPS or DSS session can use a frame size greater than the MTU on
280 - no IPS or DSS session can be in the up state unless the network
306 untagged IPS 0 a)
307 1 - 255 IPS 1 - 255 <VLANID>
310 4094 IPS 0 c)
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| /Documentation/gpu/amdgpu/display/ |
| D | trace-groups-table.csv | 29 IPS, 0x100000000
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| /Documentation/devicetree/bindings/interconnect/ |
| D | fsl,imx8m-noc.yaml | 20 The buses are based on externally licensed IPs such as ARM NIC-301 and
22 interconnect IPs into imx SOCs.
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| /Documentation/devicetree/bindings/sound/ |
| D | st,sti-asoc-card.txt | 48 - st,tdm-mode: to declare to set TDM mode for unireader and uniplayer IPs.
49 Only compartible with IPs in charge of the external I2S/TDM bus.
98 2) sti-sas-codec: internal audio codec IPs driver
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| /Documentation/scsi/ |
| D | scsi-parameters.rst | 43 ips= [HW,SCSI] Adaptec / IBM ServeRAID controller
44 See header of drivers/scsi/ips.c.
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| D | ChangeLog.ips | 34 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail )
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| /Documentation/devicetree/bindings/soc/imx/ |
| D | fsl,aips-bus.yaml | 14 AHB bus and peripherals with the lower bandwidth IP Slave (IPS)
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| /Documentation/trace/ |
| D | fprobe.rst | 50 unsigned long ips[] = { 0x.... };
52 register_fprobe_ips(&fp, ips, ARRAY_SIZE(ips));
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| /Documentation/devicetree/bindings/soc/amlogic/ |
| D | amlogic,canvas.yaml | 19 Many IPs within Amlogic SoCs rely on canvas indexes to read/write pixel data
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| /Documentation/devicetree/bindings/display/panel/ |
| D | focaltech,gpt3.yaml | 7 title: Focaltech GPT3 3.0" (640x480 pixels) IPS LCD panel
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| D | leadtek,ltk035c5444t.yaml | 7 title: Leadtek ltk035c5444t 3.5" (640x480 pixels) 24-bit IPS LCD panel
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| D | abt,y030xx067a.yaml | 7 title: Asia Better Technology 3.0" (320x480 pixels) 24-bit IPS LCD panel
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| D | fascontek,fs035vg158.yaml | 7 title: Fascontek FS035VG158 3.5" (640x480 pixels) 24-bit IPS LCD panel
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| D | anbernic,rg35xx-plus-panel.yaml | 7 title: Anbernic RG35XX series (WL-355608-A8) 3.5" 640x480 24-bit IPS LCD panel
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| D | panel-simple-dsi.yaml | 35 # JDI FHD_R63452 1080x1920 5.2" IPS LCD Panel
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| /Documentation/devicetree/bindings/regulator/ |
| D | qcom,sdm845-refgen-regulator.yaml | 14 voltage for on-chip IPs (like PHYs) on some Qualcomm SoCs.
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| /Documentation/devicetree/bindings/arm/ |
| D | arm,corstone1000.yaml | 20 video, audio and machine learning at the edge System and security IPs to build
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| /Documentation/devicetree/bindings/media/ |
| D | coda.yaml | 13 Coda codec IPs are present in i.MX SoCs in various versions,
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| /Documentation/devicetree/bindings/thermal/ |
| D | qcom-lmh.yaml | 16 programmed by software for certain IPs like CPU.
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | mux.txt | 20 Some clock controller IPs do not allow a value of zero to be programmed
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | omap.txt | 4 IPs present in the SoC.
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