| /Documentation/devicetree/bindings/arm/omap/ |
| D | crossbar.txt | 13 - ti,max-irqs: Total number of irqs available at the parent interrupt controller.
17 - ti,irqs-reserved: List of the reserved irq lines that are not muxed using
23 - ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for
24 SOC-specific hard-wiring of those irqs which unexpectedly bypasses the
25 crossbar. These irqs have a crossbar register, but still cannot be used.
27 - ti,irqs-safe-map: integer which maps to a safe configuration to use
34 ti,max-irqs = <160>;
37 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
38 ti,irqs-skip = <10 133 139 140>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | atmel,aic.yaml | 49 atmel,external-irqs:
51 description: u32 array of external irqs.
62 atmel,external-irqs:
67 atmel,external-irqs:
76 - atmel,external-irqs
87 atmel,external-irqs = <31>;
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| D | st,stih407-irq-syscfg.yaml | 7 title: STMicroelectronics STi System Configuration Controlled IRQs
14 Management), and PL310 L2 Cache IRQs are controlled using System
26 description: Array of IRQs to enable.
40 description: External IRQs can be inverted at will. This property inverts
41 these three IRQs using bitwise logic, each one being encoded respectively
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| D | mrvl,intc.yaml | 22 - mrvl,intc-nr-irqs
86 mrvl,intc-nr-irqs:
111 mrvl,intc-nr-irqs = <64>;
121 mrvl,intc-nr-irqs = <2>;
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| D | fsl,irqsteer.yaml | 60 u32 value representing the output channel that all input IRQs should be
63 fsl,num-irqs:
78 - fsl,num-irqs
110 fsl,num-irqs = <64>;
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| D | mstar,mst-intc.yaml | 33 mstar,irqs-map-range:
50 - mstar,irqs-map-range
62 mstar,irqs-map-range = <0 63>;
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| D | brcm,bcm6345-l1-intc.txt | 13 peripheral IRQs to be routed to any CPU
22 2-4 status words to determine which IRQs are pending
28 the number of supported IRQs is inferred from the size argument
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| D | mti,cpu-interrupt-controller.yaml | 11 IRQs from a devicetree file and create a irq_domain for IRQ controller.
13 With the irq_domain in place we can describe how the 8 IRQs are wired to the
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| D | brcm,bcm7038-l1-intc.yaml | 21 peripheral IRQs to be routed to any CPU
28 2-5 status words to determine which IRQs are pending
48 the number of supported IRQs is inferred from the size argument
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| D | apple,aic2.yaml | 18 - Level-triggered hardware IRQs wired to SoC blocks
22 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
52 - HW IRQs: interrupt number
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| D | apple,aic.yaml | 19 - Level-triggered hardware IRQs wired to SoC blocks
26 - Automatic prioritization (single event/ack register per CPU, lower IRQs =
65 - HW IRQs: interrupt number
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| D | microchip,pic32-evic.txt | 33 - microchip,external-irqs: u32 array of external interrupts with software
45 microchip,external-irqs = <3 8 13 18 23>;
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| D | ti,pruss-intc.yaml | 22 The property "ti,irqs-reserved" is used for denoting the connection
85 ti,irqs-reserved:
161 ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
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| D | faraday,ftintc010.txt | 14 IRQs. The bindings follows the standard binding for controllers
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| /Documentation/power/ |
| D | suspend-and-interrupts.rst | 9 Suspending and Resuming Device IRQs
12 Device interrupt request lines (IRQs) are generally disabled during system
21 interrupt handlers for shared IRQs that device drivers implementing them were
29 Device IRQs are re-enabled during system resume, right before the "early" phase
91 not executed for system wakeup IRQs. They are only executed for IRQF_NO_SUSPEND
92 IRQs at that time, but those IRQs should not be configured for system wakeup
126 Second, both enable_irq_wake() and IRQF_NO_SUSPEND apply to entire IRQs and not
133 must be able to discern spurious IRQs from genuine wakeup events (signalling
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-auxiliary | 1 What: /sys/bus/auxiliary/devices/.../irqs/
5 The /sys/devices/.../irqs directory contains a variable set of
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| /Documentation/arch/arm/ |
| D | interrupts.rst | 18 The 2.5 kernels will be having major changes to the way IRQs are handled.
39 SA1111 IRQ handler, SA1111 IRQs can hold off SMC9196 IRQs indefinitely.
50 SA11x0 IRQs are handled by two separate "chip" structures, one for
81 - required. May be the same function as mask for IRQs
89 IRQs that use this 'irqchip'. Generally expected to re-trigger
167 hardware based. Mixing level-based and edge-based IRQs on the same
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| /Documentation/ABI/stable/ |
| D | sysfs-bus-fsl-mc | 16 disable the DPRC IRQs on which automatic rescan
18 will enable the DPRC IRQs.
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| /Documentation/devicetree/bindings/mfd/ |
| D | bfticu.txt | 4 Its main functionality is to collect IRQs from the whole chassis and signals
10 - interrupts: the main IRQ line to signal the collected IRQs
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| /Documentation/admin-guide/pm/ |
| D | suspend-flows.rst | 77 3. Suspending devices and reconfiguring IRQs.
96 IRQs associated with system wakeup devices are "armed" so that the resume
137 2. Resuming devices and restoring the working-state configuration of IRQs.
146 The working-state configuration of IRQs is restored after the *noirq* resume
180 3. Suspending devices and reconfiguring IRQs.
183 described `above <s2idle_suspend_>`_, but the arming of IRQs for system
215 This means that all tasks are migrated away from those CPUs and all IRQs are
257 4. Resuming devices and restoring the working-state configuration of IRQs.
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| /Documentation/core-api/irq/ |
| D | index.rst | 2 IRQs title
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| /Documentation/trace/ |
| D | osnoise-tracer.rst | 8 NMIs, IRQs, SoftIRQs, and any other system thread can cause noise to the
19 IRQs, and SoftIRQs cannot interfere with the hwlatd thread. Hence, the
29 similar loop with preemption, SoftIRQs and IRQs enabled, thus allowing
34 interference. The interference counter for NMI, IRQs, SoftIRQs, and
59 # _-----=> irqs-off
131 - OSNOISE_IRQ_DISABLE: disable IRQs while running the osnoise workload,
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| /Documentation/translations/zh_CN/core-api/irq/ |
| D | index.rst | 13 IRQs title
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| /Documentation/tools/rtla/ |
| D | common_osnoise_description.rst | 3 time in a loop while with preemption, softirq and IRQs enabled, thus
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| /Documentation/devicetree/bindings/gpio/ |
| D | gpio-xgene-sb.txt | 34 - apm,nr-irqs: Optional, specify number of interrupt pins.
53 apm,nr-irqs = <6>;
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