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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,orion-intc.txt | 1 Marvell Orion SoC interrupt controllers
3 * Main interrupt controller
7 - reg: base address(es) of interrupt registers starting with CAUSE register
8 - interrupt-controller: identifies the node as an interrupt controller
9 - #interrupt-cells: number of cells to encode an interrupt source, shall be 1
11 The interrupt sources map to the corresponding bits in the interrupt
18 intc: interrupt-controller {
20 interrupt-controller;
21 #interrupt-cells = <1>;
26 * Bridge interrupt controller
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| D | renesas,rzg2l-irqc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,rzg2l-irqc.yaml#
7 title: Renesas RZ/G2L (and alike SoC's) Interrupt Controller (IA55)
14 IA55 performs various interrupt controls including synchronization for the external
16 interrupts output by each IP. And it notifies the interrupt to the GIC
18 - GPIO pins used as external interrupt input pins, mapped to 32 GIC SPI interrupts
35 '#interrupt-cells':
37 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
44 interrupt-controller: true
52 - description: NMI interrupt
53 - description: IRQ0 interrupt
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| D | snps,dw-apb-ictl.txt | 1 Synopsys DesignWare APB interrupt controller (dw_apb_ictl)
3 Synopsys DesignWare provides interrupt controller IP for APB known as
4 dw_apb_ictl. The IP is used as secondary interrupt controller in some SoCs with
5 APB bus, e.g. Marvell Armada 1500. It can also be used as primary interrupt
12 - interrupt-controller: identifies the node as an interrupt controller
13 - #interrupt-cells: number of cells to encode an interrupt-specifier, shall be 1
15 Additional required property when it's used as secondary interrupt controller:
16 - interrupts: interrupt reference to primary interrupt controller
18 The interrupt sources map to the corresponding bits in the interrupt
27 /* dw_apb_ictl is used as secondary interrupt controller */
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| D | samsung,exynos4210-combiner.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/samsung,exynos4210-combiner.yaml#
7 title: Samsung Exynos SoC Interrupt Combiner Controller
13 Samsung's Exynos4 architecture includes a interrupt combiner controller which
14 can combine interrupt sources as a group and provide a single interrupt
15 request for the group. The interrupt request from each group are connected to
16 a parent interrupt controller, such as GIC in case of Exynos4210.
18 The interrupt combiner controller consists of multiple combiners. Up to eight
19 interrupt sources can be connected to a combiner. The combiner outputs one
20 combined interrupt for its eight interrupt sources. The combined interrupt is
21 usually connected to a parent interrupt controller.
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| D | marvell,icu.txt | 1 Marvell ICU Interrupt Controller
4 The Marvell ICU (Interrupt Consolidation Unit) controller is
5 responsible for collecting all wired-interrupt sources in the CP and
6 communicating them to the GIC in the AP, the unit translates interrupt
17 Subnodes: Each group of interrupt is declared as a subnode of the ICU,
28 - #interrupt-cells: Specifies the number of cells needed to encode an
29 interrupt source. The value shall be 2.
31 The 1st cell is the index of the interrupt in the ICU unit.
33 The 2nd cell is the type of the interrupt. See arm,gic.txt for
36 - interrupt-controller: Identifies the node as an interrupt
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| D | interrupts.txt | 1 Specifying interrupt information for devices
4 1) Interrupt client nodes
11 properties contain a list of interrupt specifiers, one per output interrupt. The
12 format of the interrupt specifier is determined by the interrupt controller to
16 interrupt-parent = <&intc1>;
19 The "interrupt-parent" property is used to specify the controller to which
20 interrupts are routed and contains a single phandle referring to the interrupt
22 interrupt client node or in any of its parent nodes. Interrupts listed in the
23 "interrupts" property are always in reference to the node's interrupt parent.
26 to reference multiple interrupt parents or a different interrupt parent than
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| D | qca,ath79-misc-intc.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller
3 The MISC interrupt controller is a secondary controller for lower priority
4 interrupt.
10 - interrupts: Interrupt specifier for the controllers interrupt.
11 - interrupt-controller : Identifies the node as an interrupt controller
12 - #interrupt-cells : Specifies the number of cells needed to encode interrupt
19 Interrupt Controllers bindings used by client devices.
23 interrupt-controller@18060010 {
27 interrupt-parent = <&cpuintc>;
30 interrupt-controller;
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| D | fsl,ls-extirq.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-extirq.yaml#
7 title: Freescale Layerscape External Interrupt Controller
14 LX216xA) support inverting the polarity of certain external interrupt
34 '#interrupt-cells':
40 interrupt-controller: true
45 Specifies the Interrupt Polarity Control Register (INTPCR) in the
46 SCFG or the External Interrupt Control Register (IRQCR) in the ISC.
48 interrupt-map:
51 interrupt-map-mask: true
55 - '#interrupt-cells'
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| D | nxp,lpc3220-mic.txt | 1 * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers
6 - interrupt-controller: identifies the node as an interrupt controller.
7 - #interrupt-cells: the number of cells to define an interrupt, should be 2.
17 - interrupts: empty for MIC interrupt controller, cascaded MIC
22 /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */
23 mic: interrupt-controller@40008000 {
26 interrupt-controller;
27 #interrupt-cells = <2>;
30 sic1: interrupt-controller@4000c000 {
33 interrupt-controller;
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| D | intel,ixp4xx-interrupt.yaml | 5 $id: http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#
8 title: Intel IXP4xx XScale Networking Processors Interrupt Controller
14 This interrupt controller is found in the Intel IXP4xx processors.
19 The distinct IXP4xx families with different interrupt controller
28 - intel,ixp42x-interrupt
29 - intel,ixp43x-interrupt
30 - intel,ixp45x-interrupt
31 - intel,ixp46x-interrupt
36 interrupt-controller: true
38 '#interrupt-cells':
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| D | brcm,bcm2835-armctrl-ic.txt | 1 BCM2835 Top-Level ("ARMCTRL") Interrupt Controller
3 The BCM2835 contains a custom top-level interrupt controller, which supports
4 72 interrupt sources using a 2-level register scheme. The interrupt
8 The BCM2836 contains the same interrupt controller with the same
9 interrupts, but the per-CPU interrupt controller is the root, and an
10 interrupt there indicates that the ARMCTRL has an interrupt to handle.
17 - interrupt-controller : Identifies the node as an interrupt controller
18 - #interrupt-cells : Specifies the number of cells needed to encode an
19 interrupt source. The value shall be 2.
21 The 1st cell is the interrupt bank; 0 for interrupts in the "IRQ basic
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| D | loongson,liointc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
7 title: Loongson Local I/O Interrupt Controller
13 This interrupt controller is found in the Loongson-3 family of chips and
14 Loongson-2K series chips, as the primary package interrupt controller which
15 can route local I/O interrupt to interrupt lines of cores.
18 2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
19 need to define two nodes in dts{i} to describe the "0-31" and "32-61" interrupt
23 - $ref: /schemas/interrupt-controller.yaml#
43 interrupt-controller: true
47 Interrupt source of the CPU interrupts.
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| D | microchip,lan966x-oic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/microchip,lan966x-oic.yaml#
7 title: Microchip LAN966x outband interrupt controller
13 - $ref: /schemas/interrupt-controller.yaml#
16 The Microchip LAN966x outband interrupt controller (OIC) maps the internal
17 interrupt sources of the LAN966x device to an external interrupt.
18 When the LAN966x device is used as a PCI device, the external interrupt is
19 routed to the PCI interrupt.
25 '#interrupt-cells':
28 interrupt-controller: true
38 - '#interrupt-cells'
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| D | riscv,aplic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
7 title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
13 The RISC-V advanced interrupt architecture (AIA) defines an advanced
14 platform level interrupt controller (APLIC) for handling wired interrupts
19 interrupt sources connect to the root APLIC domain and a parent APLIC
20 domain can delegate interrupt sources to it's child APLIC domains. There
24 - $ref: /schemas/interrupt-controller.yaml#
36 interrupt-controller: true
38 "#interrupt-cells":
52 message signaled interrupt controller (IMSIC). If both "msi-parent" and
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| D | img,pdc-intc.txt | 1 * ImgTec Powerdown Controller (PDC) Interrupt Controller Binding
4 representation of a PDC IRQ controller. This has a number of input interrupt
5 lines which can wake the system, and are passed on through output interrupt
10 - compatible: Specifies the compatibility list for the interrupt controller.
16 - interrupt-controller: The presence of this property identifies the node
17 as an interrupt controller. No property value shall be defined.
19 - #interrupt-cells: Specifies the number of cells needed to encode an
20 interrupt source. The type shall be a <u32> and the value shall be 2.
26 - interrupts: List of interrupt specifiers. The first specifier shall be the
27 shared SysWake interrupt, and remaining specifies shall be PDC peripheral
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| D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller
4 The Abilis TB10x SOC contains a custom interrupt controller. It performs
5 one-to-one mapping of external interrupt sources to CPU interrupts and
13 - interrupt-congroller: Identifies the node as an interrupt controller.
14 - #interrupt cells: Specifies the number of cells used to encode an interrupt
16 - interrupts: Specifies the list of interrupt lines which are handled by
17 the interrupt controller in the parent controller's notation. Interrupts
23 intc: interrupt-controller { /* Parent interrupt controller */
24 interrupt-controller;
25 #interrupt-cells = <1>; /* For example below */
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| D | snps,archs-idu-intc.txt | 1 * ARC-HS Interrupt Distribution Unit
3 This optional 2nd level interrupt controller can be used in SMP configurations
10 - interrupt-controller: This is an interrupt controller.
11 - #interrupt-cells: Must be <1> or <2>.
14 Number N of the particular interrupt line of IDU corresponds to the line N+24
15 of the core interrupt controller.
23 When no second cell is specified, the interrupt is assumed to be level
26 The interrupt controller is accessed via the special ARC AUX register
30 core_intc: core-interrupt-controller {
32 interrupt-controller;
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| D | brcm,bcm7120-l2-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
13 This interrupt controller hardware is a second level interrupt controller that
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
17 Such an interrupt controller has the following hardware design:
19 - outputs multiple interrupts signals towards its interrupt controller parent
22 directly output an interrupt signal towards the interrupt controller parent,
23 or if they will output an interrupt signal at this 2nd level interrupt
30 - not all bits within the interrupt controller actually map to an interrupt
34 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
36 0 -----[ MUX ] ------------|==========> GIC interrupt 75
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| D | riscv,cpu-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/riscv,cpu-intc.yaml#
7 title: RISC-V Hart-Level Interrupt Controller (HLIC)
13 to the core. Every interrupt is ultimately routed through a hart's HLIC
16 The RISC-V supervisor ISA manual specifies three interrupt sources that are
17 attached to every HLIC namely software interrupts, the timer interrupt, and
19 cores. The timer interrupt comes from an architecturally mandated real-
22 the HLIC, which are routed via the platform-level interrupt controller
26 required to have a HLIC with these three interrupt sources present. Since
27 the interrupt map is defined by the ISA it's not listed in the HLIC's device
28 tree entry, though external interrupt controllers (like the PLIC, for
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| D | arm,vic.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
7 title: ARM Vectored Interrupt Controller
13 One or more Vectored Interrupt Controllers (VIC's) can be connected in an
14 ARM system for interrupt routing. For multiple controllers they can either
18 - $ref: /schemas/interrupt-controller.yaml#
27 interrupt-controller: true
29 "#interrupt-cells":
33 VIC has no configuration options for interrupt sources. The single
34 cell defines the interrupt number.
44 A one cell big bit mask of valid interrupt sources. Each bit
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mpic.txt | 2 Freescale MPIC Interrupt Controller Node
6 The Freescale MPIC interrupt controller is found on all PowerQUICC
9 additional cells in the interrupt specifier defining interrupt type
29 - interrupt-controller
32 Definition: Specifies that this node is an interrupt
35 - #interrupt-cells
38 Definition: Shall be 2 or 4. A value of 2 means that interrupt
39 specifiers do not contain the interrupt-type or type-specific
52 the boot program has initialized all interrupt source
57 that any initialization related to interrupt sources shall
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| /Documentation/devicetree/bindings/net/wireless/ |
| D | qcom,ath11k.yaml | 33 interrupt-names:
105 - description: misc-pulse1 interrupt events
106 - description: misc-latch interrupt events
107 - description: sw exception interrupt events
108 - description: watchdog interrupt events
109 - description: interrupt event for ring CE0
110 - description: interrupt event for ring CE1
111 - description: interrupt event for ring CE2
112 - description: interrupt event for ring CE3
113 - description: interrupt event for ring CE4
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| /Documentation/devicetree/bindings/pci/ |
| D | xlnx,xdma-host.yaml | 38 - description: interrupt asserted when miscellaneous interrupt is received.
39 - description: msi0 interrupt asserted when an MSI is received.
40 - description: msi1 interrupt asserted when an MSI is received.
42 interrupt-names:
48 interrupt-map-mask:
55 interrupt-map:
58 "#interrupt-cells":
61 interrupt-controller:
62 description: identifies the node as an interrupt controller
65 interrupt-controller: true
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| D | xlnx,nwl-pcie.yaml | 14 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
34 - description: interrupt asserted when miscellaneous interrupt is received
35 - description: unused interrupt(dummy)
36 - description: interrupt asserted when a legacy interrupt is received
37 - description: msi1 interrupt asserted when an MSI is received
38 - description: msi0 interrupt asserted when an MSI is received
40 interrupt-names:
48 interrupt-map-mask:
55 "#interrupt-cells":
61 interrupt-map:
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| /Documentation/devicetree/bindings/arm/freescale/ |
| D | fsl,vf610-mscm-ir.txt | 1 Freescale Vybrid Miscellaneous System Control - Interrupt Router
4 block of registers which control the interrupt router. The interrupt router
5 allows to configure the recipient of each peripheral interrupt. Furthermore
12 - reg: the register range of the MSCM Interrupt Router
15 - interrupt-controller: Identifies the node as an interrupt controller
16 - #interrupt-cells: Two cells, interrupt number and cells.
17 The hardware interrupt number according to interrupt
18 assignment of the interrupt router is required.
23 mscm_ir: interrupt-controller@40001800 {
27 interrupt-controller;
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