| /Documentation/networking/ |
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| /Documentation/virt/kvm/x86/ |
| D | running-nested-guests.rst | 19 | L1 (Guest Hypervisor) |
33 - L1 – level-1 guest; a VM running on L0; also called the "guest
36 - L2 – level-2 guest; a VM running on L1, this is the "nested guest"
45 metal, running the LPAR hypervisor), L1 (host hypervisor), L2
49 L1, and L2) for all architectures; and will largely focus on
148 able to start an L1 guest with::
175 2. The guest hypervisor (L1) must be provided with the ``sie`` CPU
179 3. Now the KVM module can be loaded in the L1 (guest hypervisor)::
187 Migrating an L1 guest, with a *live* nested guest in it, to another
191 On AMD systems, once an L1 guest has started an L2 guest, the L1 guest
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| D | nested-vmx.rst | 33 L0, the guest hypervisor, which we call L1, and its nested guest, which we
65 As a VMX implementation, nested VMX presents a VMCS structure to L1.
73 The name "vmcs12" refers to the VMCS that L1 builds for L2. In the code we
74 also have "vmcs01", the VMCS that L0 built for L1, and "vmcs02" is the VMCS
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| /Documentation/devicetree/bindings/regulator/ |
| D | qcom,smd-rpm-regulator.yaml | 27 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
30 For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9,
33 For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22,
36 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob
38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
44 For pm8909, s1, s2, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
47 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
50 For pm8937, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
53 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
57 For pm8950 and pm8953, s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6,
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| D | qcom,rpmh-regulator.yaml | 164 vdd-l1-l8-supply: true
179 vdd-l1-l6-l7-supply: true
196 vdd-l1-l9-l10-supply: true
211 vdd-l1-l4-l12-l15-supply: true
250 vdd-l1-l2-supply: true
264 vdd-l1-l8-l11-supply: true
280 vdd-l1-supply: true
296 vdd-l1-l4-supply: true
313 vdd-l1-l12-supply: true
338 vdd-l1-l4-l10-supply: true
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| D | qcom,rpm-regulator.yaml | 19 For pm8058 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15,
23 For pm8901 l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3,
26 For pm8921 s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
31 For pm8018 s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | brcm,bcm6345-l1-intc.txt | 10 - Most onchip peripherals are wired directly to an L1 input
26 - compatible: should be "brcm,bcm<soc>-l1-intc", "brcm,bcm6345-l1-intc"
46 compatible = "brcm,bcm63168-l1-intc", "brcm,bcm6345-l1-intc";
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| D | brcm,bcm7038-l1-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
18 - Most onchip peripherals are wired directly to an L1 input
43 const: brcm,bcm7038-l1-intc
63 If present, this means the L1 controller can be used as a
85 compatible = "brcm,bcm7038-l1-intc";
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| D | brcm,bcm2836-l1-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm2836-l1-intc.yaml#
24 const: brcm,bcm2836-l1-intc
45 compatible = "brcm,bcm2836-l1-intc";
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| /Documentation/arch/powerpc/ |
| D | kvm-nested.rst | 12 hypervisor has implemented them. The terms L0, L1, and L2 are used to
14 that would normally be called the "host" or "hypervisor". L1 is a
17 and controlled by L1 acting as a hypervisor.
22 Linux/KVM has had support for Nesting as an L0 or L1 since 2018
31 The L1 code was added::
39 call made by the L1 to tell the L0 to start an L2 vCPU with the given
42 the L1 by the L0. The full L2 vCPU state is always transferred from
43 and to L1 when the L2 is run. The L0 doesn't keep any state on the L2
44 vCPU (except in the short sequence in the L0 on L1 -> L2 entry and L2
45 -> L1 exit).
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| /Documentation/locking/ |
| D | lockdep-design.rst | 22 dependency can be understood as lock order, where L1 -> L2 suggests that
23 a task is attempting to acquire L2 while holding L1. From lockdep's
24 perspective, the two locks (L1 and L2) are not necessarily related; that
145 <L1> -> <L2>
146 <L2> -> <L1>
521 L1 -> L2
523 , which means lockdep has seen L1 held before L2 held in the same context at runtime.
524 And in deadlock detection, we care whether we could get blocked on L2 with L1 held,
525 IOW, whether there is a locker L3 that L1 blocks L3 and L2 gets blocked by L3. So
526 we only care about 1) what L1 blocks and 2) what blocks L2. As a result, we can combine
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| D | rt-mutex-design.rst | 47 grab lock L1 (owned by C)
139 Mutexes: L1, L2, L3, L4
141 A owns: L1
142 B blocked on L1
152 E->L4->D->L3->C->L2->B->L1->A
159 F->L5->B->L1->A
168 +->B->L1->A
180 G->L2->B->L1->A
188 G-+ +->B->L1->A
230 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
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| D | percpu-rw-semaphore.rst | 10 is bouncing between L1 caches of the cores, causing performance
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| /Documentation/translations/it_IT/locking/ |
| D | lockdep-design.rst | 21 possono essere interpretate come il loro ordine; per esempio L1 -> L2 suggerisce
22 che un processo cerca di acquisire L2 mentre già trattiene L1. Dal punto di
23 vista di lockdep, i due blocchi (L1 ed L2) non sono per forza correlati: quella
143 <L1> -> <L2>
144 <L2> -> <L1>
531 L1 -> L2
533 Questo significa che lockdep ha visto acquisire L1 prima di L2 nello stesso
535 interessa sapere se possiamo rimanere bloccati da L2 mentre L1 viene trattenuto.
537 da L1 e un L2 che viene bloccato da L3. Dunque, siamo interessati a (1) quello
538 che L1 blocca e (2) quello che blocca L2. Di conseguenza, possiamo combinare
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| /Documentation/devicetree/bindings/media/ |
| D | st-rc.txt | 10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
13 - tx-mode: should be "infrared". This property specifies the L1
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| /Documentation/driver-api/ |
| D | edac.rst | 155 - CPU caches (L1 and L2)
165 For example, a cache could be composed of L1, L2 and L3 levels of cache.
166 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
174 cpu/cpu0/.. <L1 and L2 block directory>
175 /L1-cache/ce_count
179 cpu/cpu1/.. <L1 and L2 block directory>
180 /L1-cache/ce_count
186 the L1 and L2 directories would be "edac_device_block's"
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| /Documentation/devicetree/bindings/mfd/ |
| D | qcom,pm8008.yaml | 30 vdd-l1-l2-supply: true
92 - vdd-l1-l2-supply
124 vdd-l1-l2-supply = <&vreg_s8b_1p2>;
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| /Documentation/devicetree/bindings/remoteproc/ |
| D | ti,k3-dsp-rproc.yaml | 18 L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
100 - description: Address and Size of the L1 PRAM internal memory region
101 - description: Address and Size of the L1 DRAM internal memory region
119 - description: Address and Size of the L1 DRAM internal memory region
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| /Documentation/devicetree/bindings/sound/ |
| D | nvidia,tegra-audio-rt5677.yaml | 50 - DMIC L1
84 "DMIC L1", "Internal Mic 1",
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| D | rt5660.txt | 31 * DMIC L1
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| D | rt5668.txt | 32 * DMIC L1
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| /Documentation/devicetree/bindings/pci/ |
| D | brcm,stb-pcie.yaml | 74 Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)
77 potentially hanging the system; "default" -- which provides L0s, L1,
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
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