| /Documentation/devicetree/bindings/interconnect/ |
| D | qcom,osm-l3.yaml | 4 $id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
7 title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
13 L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14 The OSM L3 interconnect provider aggregates the L3 bandwidth requests
22 - qcom,sc7180-osm-l3
23 - qcom,sc8180x-osm-l3
24 - qcom,sdm670-osm-l3
25 - qcom,sdm845-osm-l3
26 - qcom,sm6350-osm-l3
27 - qcom,sm8150-osm-l3
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| /Documentation/devicetree/bindings/arm/omap/ |
| D | l3-noc.txt | 1 * TI - L3 Network On Chip (NoC)
7 - compatible : Should be "ti,omap3-l3-smx" for OMAP3 family
8 Should be "ti,omap4-l3-noc" for OMAP4 family
9 Should be "ti,omap5-l3-noc" for OMAP5 family
10 Should be "ti,dra7-l3-noc" for DRA7 family
11 Should be "ti,am4372-l3-noc" for AM43 family
12 - reg: Contains L3 register address range for each noc domain.
18 compatible = "ti,omap4-l3-noc", "simple-bus";
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| /Documentation/devicetree/bindings/regulator/ |
| D | qcom,smd-rpm-regulator.yaml | 27 For pm2250, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
30 For pm6125 s1, s2, s3, s4, s5, s6, s7, s8, l1, l2, l3, l5, l6, l7, l8, l9,
33 For pm660, s1, s2, s3, s4, s5, s6, l1, l2, l3, l5, l6, l7, l8, l9, l10, l22,
36 For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob
38 For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
44 For pm8909, s1, s2, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13,
47 For pm8916, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
50 For pm8937, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10,
53 For pm8941, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
57 For pm8950 and pm8953, s1, s2, s3, s4, s5, s6, s7, l1, l2, l3, l4, l5, l6,
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| D | qcom,rpm-regulator.yaml | 19 For pm8058 l0, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15,
23 For pm8901 l0, l1, l2, l3, l4, l5, l6, s0, s1, s2, s3, s4, lvs0, lvs1, lvs2, lvs3,
26 For pm8921 s1, s2, s3, s4, s7, s8, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
31 For pm8018 s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11,
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| D | qcom,rpmh-regulator.yaml | 144 vdd-l2-l3-supply: true
165 vdd-l2-l3-supply: true
180 vdd-l2-l3-supply: true
198 vdd-l3-l5-l7-l8-supply: true
251 vdd-l3-l4-supply: true
266 vdd-l3-l4-l5-l18-supply: true
281 vdd-l2-l3-supply: true
298 vdd-l3-l5-supply: true
315 vdd-l3-l4-l5-l7-l13-supply: true
368 vdd-l3-l11-supply: true
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| /Documentation/devicetree/bindings/edac/ |
| D | apm-xgene-edac.txt | 8 L3 - L3 cache controller
24 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
39 Required properties for L3 subnode:
40 - compatible : Shall be "apm,xgene-edac-l3" or
41 "apm,xgene-edac-l3-v2".
42 - reg : First resource shall be the L3 EDAC resource.
46 "apm,xgene-edac-l3-soc" for general value reporting
104 compatible = "apm,xgene-edac-l3";
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| /Documentation/networking/ |
| D | ipvlan.rst | 13 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
36 MODE: l3 (default) | l3s | l2
42 L3 bridge mode::
61 IPvlan has two modes of operation - L2 and L3. For a given master device,
64 that in L3 mode the slaves won't receive any multicast / broadcast traffic.
65 L3 mode is more restrictive since routing is controlled from the other (mostly)
76 4.2 L3 mode:
79 In this mode TX processing up to L3 happens on the stack instance attached
88 This is very similar to the L3 mode except that iptables (conn-tracking)
89 works in this mode and hence it is L3-symmetric (L3s). This will have slightly less
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| D | bareudp.rst | 7 There are various L3 encapsulation standards using UDP being discussed to
11 The Bareudp tunnel module provides a generic L3 encapsulation support for
12 tunnelling different L3 protocols like MPLS, IP, NSH etc. inside a UDP tunnel.
30 This creates a bareudp tunnel device which tunnels L3 traffic with ethertype
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| /Documentation/admin-guide/perf/ |
| D | qcom_l3_pmu.rst | 2 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
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| D | arm_dsu_pmu.rst | 5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
7 allows counting the various events related to the L3 cache, Snoop Control Unit
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| D | xgene-pmu.rst | 6 L3 cache(s), I/O bridge(s), memory controller bridge(s) and memory
25 performance of a specific datapath. For example, agents of a L3 cache can be
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| /Documentation/devicetree/bindings/sound/ |
| D | omap-dmic.txt | 7 <L3 interconnect address, size>;
16 <0x4902e000 0x7f>; /* L3 Interconnect */
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| D | ti,omap4-mcpdm.yaml | 22 - description: L3 interconnect address
65 <0x49032000 0x7f>; /* L3 Interconnect */
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| D | omap-mcbsp.txt | 10 <L3 interconnect address, size>;
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| /Documentation/arch/x86/ |
| D | resctrl.rst | 43 Enable code/data prioritization in L3 cache allocations.
53 L2 and L3 CDP are controlled separately.
77 Cache resource(L3/L2) subdirectory contains the following files
272 # echo L3:0=f7 > schemata
369 This contains a set of files organized by L3 domain and by
370 RDT event. E.g. on a system with two L3 domains there will
380 for the L3 cache they occupy). These are named "mon_sub_L3_YY"
467 On current generation systems there is one L3 cache per socket and L2
469 isn't an architectural requirement. We could have multiple separate L3
495 on Sub-NUMA nodes share the same L3 cache and the system may report
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| /Documentation/devicetree/bindings/cache/ |
| D | socionext,uniphier-system-cache.yaml | 78 // System with L2 and L3.
89 next-level-cache = <&l3>;
92 l3: cache-controller@500c8000 {
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| D | starfive,jh8100-starlink-cache.yaml | 13 StarFive's StarLink Cache Controller manages the L3 cache shared between
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| /Documentation/locking/ |
| D | rt-mutex-design.rst | 139 Mutexes: L1, L2, L3, L4
145 C owns L3
146 D blocked on L3
152 E->L4->D->L3->C->L2->B->L1->A
166 E->L4->D->L3->C->L2-+
185 E->L4->D->L3->C-+
230 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
231 The following shows a locking order of L1->L2->L3, but may not actually
257 mutex_lock(L3);
261 mutex_unlock(L3);
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| /Documentation/devicetree/bindings/mfd/ |
| D | qcom,pm8008.yaml | 31 vdd-l3-l4-supply: true
93 - vdd-l3-l4-supply
125 vdd-l3-l4-supply = <&vreg_s1b_1p8>;
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| /Documentation/devicetree/bindings/net/ |
| D | microchip,sparx5-switch.yaml | 20 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported
24 L3 security features include source guard and reverse path
25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and
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| /Documentation/bpf/ |
| D | prog_flow_dissector.rst | 28 * ``n_proto`` - L3 protocol type, parsed out of L2 header
130 * ``jmp_table`` map that contains sub-programs for each supported L3 protocol
132 does ``bpf_tail_call`` to the appropriate L3 handler
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| /Documentation/devicetree/bindings/perf/ |
| D | starfive,jh8100-starlink-pmu.yaml | 14 shared L3 memory system. The PMU support overflow interrupt, up to
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| D | arm,dsu-pmu.yaml | 16 L3 memory system, control logic and external interfaces to form a multicore
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| /Documentation/ABI/testing/ |
| D | devlink-resource-mlxsw | 7 the chip including L2 FDB, L3 LPM, ECMP and more. The KVD
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| /Documentation/networking/device_drivers/ethernet/microsoft/ |
| D | netvsc.rst | 29 For TCP & UDP, we can switch hash level between L3 and L4 by ethtool
35 hashing. Using L3 hashing is recommended in this case.
|