Searched full:lcpll0 (Results 1 – 2 of 2) sorted by relevance
| /Documentation/devicetree/bindings/clock/ |
| D | brcm,iproc-clocks.yaml | 16 LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
28 - brcm,cygnus-lcpll0
35 - brcm,nsp-lcpll0
47 - brcm,sr-lcpll0
95 - brcm,cygnus-lcpll0
125 lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
126 pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
127 ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
128 sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
129 usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
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| /Documentation/devicetree/bindings/mfd/ |
| D | brcm,cru.yaml | 68 compatible = "brcm,nsp-lcpll0";
71 clock-output-names = "lcpll0", "pcie_phy", "sdio", "ddr_phy";
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