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/Documentation/devicetree/bindings/dma/
Darm-pl08x.yaml55 lli-bus-interface-ahb1:
59 lli-bus-interface-ahb2:
114 lli-bus-interface-ahb1;
115 lli-bus-interface-ahb2;
135 lli-bus-interface-ahb2;
Dlpc1850-dmamux.txt29 lli-bus-interface-ahb1;
30 lli-bus-interface-ahb2;
/Documentation/devicetree/bindings/dma/stm32/
Dst,stm32-dma3.yaml94 0x2: at LLI level, the transfer complete event is generated at the end
95 of the LLI transfer
96 including the update of the LLI if any
98 end of the last LLI
/Documentation/devicetree/bindings/clock/
Dsamsung,exynos5433-clock.yaml30 # CMU_CPIF which generates clocks for LLI (Low Latency Interface) IP