Searched full:lpddr4 (Results 1 – 8 of 8) sorted by relevance
| /Documentation/devicetree/bindings/memory-controllers/ddr/ |
| D | jedec,lpddr4.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
7 title: LPDDR4 SDRAM compliant to JEDEC JESD209-4
18 - pattern: "^lpddr4-[0-9a-f]{2},[0-9a-f]{4}$"
19 - const: jedec,lpddr4
31 compatible = "lpddr4-ff,0100", "jedec,lpddr4";
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| D | jedec,lpddr-channel.yaml | 23 - jedec,lpddr4-channel
85 const: jedec,lpddr4-channel
89 $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml#
128 compatible = "jedec,lpddr4-channel";
132 compatible = "lpddr4-05,0301", "jedec,lpddr4";
140 compatible = "lpddr4-05,0301", "jedec,lpddr4";
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| /Documentation/devicetree/bindings/memory-controllers/ |
| D | rockchip,rk3399-dmc.yaml | 91 srpd_lite_idle * 1024 DFI clock cycles. This parameter is for LPDDR4
225 When the DRAM type is LPDDR4, this parameter defines the ODT disable
233 When the DRAM type is LPDDR4, this parameter defines the DRAM side drive
241 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
249 When the DRAM type is LPDDR4, this parameter defines the DRAM side ODT on
257 When the DRAM type is LPDDR4, this parameter defines the PHY side CA line
265 When the DRAM type is LPDDR4, this parameter defines the PHY side clock
273 When the DRAM type is LPDDR4, this parameter defines the PHY side DQ line
281 When the DRAM type is LPDDR4, this parameter defines the PHY side ODT
308 srpd_lite_idle nanoseconds. This parameter is for LPDDR4 only.
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| D | xlnx,versal-ddrmc-edac.yaml | 14 The integrated DDR Memory Controllers (DDRMCs) support both DDR4 and LPDDR4/
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| D | nvidia,tegra186-mc.yaml | 15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
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| /Documentation/devicetree/bindings/soc/renesas/ |
| D | renesas,rzv2m-pwc.yaml | 13 - on/off signal generation for the LPDDR4 core power supply (LPVDD)
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| /Documentation/devicetree/bindings/regulator/ |
| D | renesas,raa215300.yaml | 15 and LPDDR4 memory power requirements. The internally compensated regulators,
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| /Documentation/devicetree/bindings/arm/ |
| D | fsl.yaml | 1049 - fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
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