Searched full:lane (Results 1 – 25 of 107) sorted by relevance
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| /Documentation/devicetree/bindings/usb/ |
| D | onnn,nb7vpq904m.yaml | 48 An array of physical data lane indexes. Position determines how
51 Lane number represents the following
52 - 0 is RX2 lane
53 - 1 is TX2 lane
54 - 2 is TX1 lane
55 - 3 is RX1 lane
66 - Port A to RX2 lane
67 - Port B to TX2 lane
68 - Port C to TX1 lane
69 - Port D to RX1 lane
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| /Documentation/devicetree/bindings/media/i2c/ |
| D | st,st-mipid02.yaml | 17 CSI-2 first input port is a dual lane 800Mbps per lane whereas CSI-2
18 second input port is a single lane 800Mbps. Both ports support clock
19 and data lane polarity swap. First port also supports data lane swap.
65 Single-lane operation shall be <1> or <2> .
66 Dual-lane operation shall be <1 2> or <2 1> .
70 lane-polarities:
72 Any lane can be inverted or not.
91 Single-lane operation shall be <1> or <2> .
94 lane-polarities:
96 Any lane can be inverted or not.
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| D | imx219.yaml | 60 The sensor supports either two-lane, or four-lane operation.
61 If this property is omitted four-lane operation is assumed.
62 For two-lane operation the property must be set to <1 2>.
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| D | tc358743.txt | 16 - data-lanes: should be <1 2 3 4> for four-lane operation,
17 or <1 2> for two-lane operation
23 is half of the bps per lane due to DDR transmission.
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| D | thine,thp7312.yaml | 98 This property is for lane reordering between the THP7312 and the
99 SoC. The sensor supports either two-lane, or four-lane operation.
100 If this property is omitted four-lane operation is assumed. For
101 two-lane operation the property must be set to <1 2>.
141 This property is for lane reordering between the THP7312 and the imaging
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| /Documentation/devicetree/bindings/media/ |
| D | video-interfaces.yaml | 165 # Assume up to 9 physical lane indices
168 An array of physical data lane indexes. Position of an entry determines
169 the logical lane number, while the value of an entry indicates physical
170 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
171 assuming the clock lane is on hardware lane 0. If the hardware does not
172 support lane reordering, monotonically incremented values shall be used
174 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
178 # Assume up to 9 physical lane indices
181 Physical clock lane index. Position of an entry determines the logical
182 lane number, while the value of an entry indicates physical lane, e.g. for
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| D | ti,omap3isp.txt | 48 lane-polarities : lane polarity (required on CSI-2)
52 clock-lanes : the clock lane (from 1 to 3). (required on CSI-2)
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| D | qcom,msm8916-camss.yaml | 90 lane number, while the value of an entry
91 indicates physical lane index. Lane swapping
92 is supported. Physical lane indexes;
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| /Documentation/admin-guide/perf/ |
| D | dwc_pcie_pmu.rst | 20 a specified lane)
34 Lane Event counters
38 specific lane by the controller. The PMU event is selected by all of:
42 - Lane k
71 dwc_rootport_13018/rx_memory_read,lane=?/ [Kernel PMU event]
85 Lane Event Usage
88 Each lane has the same event set and to avoid generating a list of hundreds
89 of events, the user need to specify the lane ID explicitly, e.g.::
91 $# perf stat -a -e dwc_rootport_13018/rx_memory_read,lane=4/
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| /Documentation/devicetree/bindings/phy/ |
| D | phy-mvebu-comphy.txt | 20 * Lane 1 (PCIe/GbE)
21 * Lane 0 (USB3/GbE)
22 * Lane 2 (SATA/USB3)
35 A sub-node is required for each comphy lane provided by the comphy.
39 - reg: COMPHY lane number.
41 input port to use for a given comphy lane.
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| D | phy-rockchip-usbdp.yaml | 45 - const: lane
49 rockchip,dp-lane-mux:
57 determines the DisplayPort (DP) lane index, while the value of an entry
58 indicates physical Type-C lane. The supported DP lanes number are 2 or 4.
59 e.g. for 2 lanes DP lanes map, we could have "rockchip,dp-lane-mux = <2,
61 lane3. For 4 lanes DP lanes map, we could have "rockchip,dp-lane-mux =
85 When select the DP lane mapping will request its phandle.
143 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
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| D | phy-cadence-sierra.yaml | 75 Each group of PHY lanes with a single master lane should be represented as
76 a sub-node. Note that the actual configuration of each lane is determined
81 The master lane number. This is the lowest numbered lane in the lane group.
89 Contains list of resets, one per lane, to get all the link lanes out of reset.
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| D | nvidia,tegra124-xusb-padctl.yaml | 15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
27 In addition to per-lane configuration, USB 3.0 ports may require additional
31 device tree node. Each lane exposed by the pad will be represented by its
32 own subnode and can be referenced by users of the lane using the standard
117 description: Function selection for this lane.
129 description: Function selection for this lane.
141 description: Function selection for this lane.
161 description: Function selection for this lane.
189 description: Function selection for this lane.
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| D | phy-armada38x-comphy.txt | 22 A sub-node is required for each comphy lane provided by the comphy.
26 - reg: comphy lane number.
28 input port to use for a given comphy lane.
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| D | nvidia,tegra210-xusb-padctl.yaml | 15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
27 In addition to per-lane configuration, USB 3.0 ports may require additional
31 device tree node. Each lane exposed by the pad will be represented by its
32 own subnode and can be referenced by users of the lane using the standard
115 description: Function selection for this lane.
127 description: Function selection for this lane.
139 description: Function selection for this lane.
151 description: Function selection for this lane.
179 description: Function selection for this lane.
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| D | nvidia,tegra186-xusb-padctl.yaml | 15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
27 In addition to per-lane configuration, USB 3.0 ports may require additional
31 device tree node. Each lane exposed by the pad will be represented by its
32 own subnode and can be referenced by users of the lane using the standard
120 description: Function selection for this lane.
132 description: Function selection for this lane.
144 description: Function selection for this lane.
172 description: Function selection for this lane.
192 description: Function selection for this lane.
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| D | rockchip,rk3588-hdptx-phy.yaml | 42 - description: LANE reset line
52 - const: lane
91 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", "lcpll";
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| D | nvidia,tegra194-xusb-padctl.yaml | 15 signals) which connect directly to pins/pads on the SoC package. Each lane
18 and thus contains any logic common to all its lanes. Each lane can be
27 In addition to per-lane configuration, USB 3.0 ports may require additional
31 device tree node. Each lane exposed by the pad will be represented by its
32 own subnode and can be referenced by users of the lane using the standard
115 description: Function selection for this lane.
127 description: Function selection for this lane.
139 description: Function selection for this lane.
151 description: Function selection for this lane.
171 description: Function selection for this lane.
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| D | phy-cadence-torrent.yaml | 80 Each group of PHY lanes with a single master lane should be represented as a sub-node.
84 The master lane number. This is the lowest numbered lane in the lane group.
92 Contains list of resets, one per lane, to get all the link lanes out of reset.
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| /Documentation/devicetree/bindings/ata/ |
| D | imx-sata.yaml | 67 Since "REXT" pin is only present for first lane of i.MX8QM PHY, it's
68 calibration result will be stored, passed through second lane, and
70 calibration PHYs, although only the third lane PHY is used by SATA.
71 - description: phandle to the first lane PHY of i.MX8QM.
72 - description: phandle to the second lane PHY of i.MX8QM.
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| /Documentation/devicetree/bindings/clock/ |
| D | qcom,ipq5332-gcc.yaml | 29 - description: PCIE 2lane PHY pipe clock source
30 - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | parade,ps8622.yaml | 21 lane-count:
70 lane-count:
74 lane-count:
91 lane-count = <2>;
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| /Documentation/ABI/testing/ |
| D | sysfs-devices-platform-kunpeng_hccs | 19 lane (bool).
43 lane (bool).
74 lane_mode: (RO) the lane mode of this port (string), e.g. x8
76 cur_lane_num: (RO) current lane number of this port.
78 lane_mask: (RO) current lane mask of this port, every bit
79 indicates a lane.
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| /Documentation/devicetree/bindings/pci/ |
| D | mvebu-pci.txt | 77 - marvell,pcie-lane: the physical PCIe lane number, for ports having
149 marvell,pcie-lane = <0>;
170 marvell,pcie-lane = <1>;
187 marvell,pcie-lane = <2>;
204 marvell,pcie-lane = <3>;
221 marvell,pcie-lane = <0>;
238 marvell,pcie-lane = <1>;
255 marvell,pcie-lane = <2>;
272 marvell,pcie-lane = <3>;
289 marvell,pcie-lane = <0>;
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| D | hisilicon,kirin-pcie.yaml | 133 pcie@0,0 { // Lane 0: PCIe switch: Bus 1, Device 0
141 pcie@0,0 { // Lane 0: upstream
149 pcie@1,0 { // Lane 4: M.2
159 pcie@5,0 { // Lane 5: Mini PCIe
169 pcie@7,0 { // Lane 6: Ethernet
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