Searched +full:loongson +full:- +full:3 (Results 1 – 25 of 67) sorted by relevance
123
| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | loongson,liointc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson Local I/O Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips and
14 Loongson-2K series chips, as the primary package interrupt controller which
17 1.The Loongson-2K0500 is a single core CPU;
18 2.The Loongson-2K0500/2K1000 has 64 device interrupt sources as inputs, so we
[all …]
|
| D | loongson,eiointc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,eiointc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson Extended I/O Interrupt Controller
10 - Binbin Zhou <zhoubinbin@loongson.cn>
13 This interrupt controller is found on the Loongson-3 family chips and
14 Loongson-2K series chips and is used to distribute interrupts directly to
18 - $ref: /schemas/interrupt-controller.yaml#
23 - loongson,ls2k0500-eiointc
[all …]
|
| D | loongson,htvec.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Vector Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This interrupt controller is found in the Loongson-3 family of chips for
18 const: loongson,htvec-1.0
28 interrupt-controller: true
30 '#interrupt-cells':
[all …]
|
| D | loongson,htpic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-3 HyperTransport Interrupt Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 - $ref: /schemas/interrupt-controller.yaml#
16 This interrupt controller is found in the Loongson-3 family of chips to transmit
21 const: loongson,htpic-1.0
32 interrupt-controller: true
[all …]
|
| /Documentation/devicetree/bindings/pci/ |
| D | loongson.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/loongson.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson PCI Host Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 PCI host controller found on Loongson PCHs and SoCs.
16 - $ref: /schemas/pci/pci-host-bridge.yaml#
21 - loongson,ls2k-pci
22 - loongson,ls7a-pci
[all …]
|
| /Documentation/devicetree/bindings/dma/ |
| D | loongson,ls1b-apbdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/loongson,ls1b-apbdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson-1 APB DMA Controller
10 - Keguang Zhang <keguang.zhang@gmail.com>
13 Loongson-1 APB DMA controller provides 3 independent channels for
19 - const: loongson,ls1b-apbdma
20 - items:
21 - enum:
[all …]
|
| /Documentation/arch/loongarch/ |
| D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 Currently, LoongArch based processors (e.g. Loongson-3A5000) can only work together
10 I/O Interrupt Controller), HTVECINTC (Hyper-Transport Vector Interrupt Controller),
11 PCH-PIC (Main Interrupt Controller in LS7A chipset), PCH-LPC (LPC Interrupt Controller
12 in LS7A chipset) and PCH-MSI (MSI Interrupt Controller).
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
15 controllers (in CPU), while PCH-PIC/PCH-LPC/PCH-MSI are controllers out of CPU (i.e.,
22 In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go
24 interrupts go to PCH-PIC/PCH-LPC/PCH-MSI and gathered by HTVECINTC, and then go
27 +-----+ +---------+ +-------+
[all …]
|
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
7 LoongArch is a new RISC ISA, which is a bit like MIPS or RISC-V. There are
8 currently 3 variants: a reduced 32-bit version (LA32R), a standard 32-bit
9 version (LA32S) and a 64-bit version (LA64). There are 4 privilege levels
22 ----
24 LoongArch has 32 GPRs ( ``$r0`` ~ ``$r31`` ); each one is 32-bit wide in LA32
25 and 64-bit wide in LA64. ``$r0`` is hard-wired to zero, and the other registers
26 are not architecturally special. (Except ``$r1``, which is hard-wired as the
30 the LoongArch ELF psABI spec, in :ref:`References <loongarch-references>`:
40 ``$r4``-``$r11`` ``$a0``-``$a7`` Argument registers No
[all …]
|
| /Documentation/devicetree/bindings/mips/loongson/ |
| D | rs780e-acpi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mips/loongson/rs780e-acpi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Loongson RS780E PCH ACPI Controller
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
13 This controller can be found in Loongson-3 systems with RS780E PCH.
17 const: loongson,rs780e-acpi
23 - compatible
24 - reg
[all …]
|
| /Documentation/translations/zh_TW/arch/loongarch/ |
| D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_TW.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
6 :Translator: Huacai Chen <chenhuacai@loongson.cn>
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片組的主中
16 斷控制器）、PCH-LPC（LS7A芯片組的LPC中斷控制器）和PCH-MSI（MSI中斷控制器）。
19 全局中斷控制器（每個芯片一個，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在這種模型裏面，IPI（Inter-Processor Interrupt）和CPU本地時鐘中斷直接發送到CPUINTC，
27 CPU串口（UARTs）中斷髮送到LIOINTC，而其他所有設備的中斷則分別發送到所連接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然後被HTVECINTC統一收集，再發送到LIOINTC，最後到達CPUINTC::
[all …]
|
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_TW.rst
6 :Translator: Huacai Chen <chenhuacai@loongson.cn>
12 LoongArch是一種新的RISC ISA，在一定程度上類似於MIPS和RISC-V。LoongArch指令集
25 ----------
32 :ref:`參考文獻 <loongarch-references-zh_TW>`:
41 ``$r4``-``$r11`` ``$a0``-``$a7`` 參數寄存器 否
42 ``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
43 ``$r12``-``$r20`` ``$t0``-``$t8`` 臨時寄存器 否
46 ``$r23``-``$r31`` ``$s0``-``$s8`` 靜態寄存器 是
[all …]
|
| /Documentation/translations/zh_CN/arch/loongarch/ |
| D | irq-chip-model.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
5 :Original: Documentation/arch/loongarch/irq-chip-model.rst
6 :Translator: Huacai Chen <chenhuacai@loongson.cn>
15 HTVECINTC（Hyper-Transport Vector Interrupt Controller）、PCH-PIC（LS7A芯片组的主中
16 断控制器）、PCH-LPC（LS7A芯片组的LPC中断控制器）和PCH-MSI（MSI中断控制器）。
19 全局中断控制器（每个芯片一个，所有核共享），而PCH-PIC/PCH-LPC/PCH-MSI是CPU外部的中
26 在这种模型里面，IPI（Inter-Processor Interrupt）和CPU本地时钟中断直接发送到CPUINTC，
27 CPU串口（UARTs）中断发送到LIOINTC，而其他所有设备的中断则分别发送到所连接的PCH-PIC/
28 PCH-LPC/PCH-MSI，然后被HTVECINTC统一收集，再发送到LIOINTC，最后到达CPUINTC::
[all …]
|
| D | introduction.rst | 1 .. SPDX-License-Identifier: GPL-2.0
3 .. include:: ../../disclaimer-zh_CN.rst
6 :Translator: Huacai Chen <chenhuacai@loongson.cn>
12 LoongArch是一种新的RISC ISA，在一定程度上类似于MIPS和RISC-V。LoongArch指令集
25 ----------
32 :ref:`参考文献 <loongarch-references-zh_CN>`:
41 ``$r4``-``$r11`` ``$a0``-``$a7`` 参数寄存器 否
42 ``$r4``-``$r5`` ``$v0``-``$v1`` 返回值 否
43 ``$r12``-``$r20`` ``$t0``-``$t8`` 临时寄存器 否
46 ``$r23``-``$r31`` ``$s0``-``$s8`` 静态寄存器 是
[all …]
|
| /Documentation/translations/zh_CN/core-api/ |
| D | packing.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/packing.rst
9 周彬彬 Binbin Zhou <zhoubinbin@loongson.cn>
13 司延腾 Yanteng Si <siyanteng@loongson.cn>
22 --------
42 --------
46 - 将一个CPU可使用的数字打包到内存缓冲区中（具有硬件约束/特殊性）。
47 - 将内存缓冲区（具有硬件约束/特殊性）解压缩为一个CPU可使用的数字。
63 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
[all …]
|
| D | circular-buffers.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
3 .. include:: ../disclaimer-zh_CN.rst
5 :Original: Documentation/core-api/circular-buffers.rst
9 周彬彬 Binbin Zhou <zhoubinbin@loongson.cn>
13 司延腾 Yanteng Si <siyanteng@loongson.cn>
41 - 生产者
42 - 消费者
53 (1) 'head'索引 - 生产者将元素插入缓冲区的位置。
55 (2) 'tail'索引 - 消费者在缓冲区中找到下一个元素的位置。
108 这里的每一个宏名义上都会返回一个介于0和buffer_size-1之间的值，但是：
[all …]
|
| /Documentation/translations/zh_CN/devicetree/ |
| D | changesets.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
8 司延腾 Yanteng Si <siyanteng@loongson.cn>
26 1. of_changeset_init() - 初始化一个变更集。
33 3. of_changeset_apply() - 将变更使用到树上。要么整个变更集被使用，要么如果有错误，
|
| D | dynamic-resolution-notes.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
4 :Original: Documentation/devicetree/dynamic-resolution-notes.rst
8 司延腾 Yanteng Si <siyanteng@loongson.cn>
19 ----------------
28 3. 使用 __local__fixups__ 节点信息以相同的量调整所有本地引用。
|
| /Documentation/translations/zh_CN/core-api/irq/ |
| D | irq-domain.rst | 1 .. include:: ../../disclaimer-zh_CN.rst
3 :Original: Documentation/core-api/irq/irq-domain.rst
7 司延腾 Yanteng Si <siyanteng@loongson.cn>
8 周彬彬 Binbin Zhou <zhoubinbin@loongson.cn>
10 .. _cn_irq-domain.rst:
58 - irq_resolve_mapping()返回一个指向给定域和hwirq号的irq_desc结构指针，
61 - irq_find_mapping()返回给定域和hwirq的Linux IRQ号，如果没有映射则返回0。
63 - irq_linear_revmap()现与irq_find_mapping()相同，已被废弃。
65 - generic_handle_domain_irq()处理一个由域和hwirq号描述的中断。
73 如在irq_chip回调中），那么可以直接从irq_data->hwirq中获得。
[all …]
|
| /Documentation/translations/zh_CN/mm/ |
| D | balance.rst | 1 .. include:: ../disclaimer-zh_CN.rst
7 司延腾 Yanteng Si <siyanteng@loongson.cn>
37 大小的生产机器上运行，即使有这个问题存在，似乎也做得不错。在2.3中，由于HIGHMEM的
40 在2.3中，区域平衡可以用两种方式之一来完成：根据区域的大小（可能是低级区域的大小），
60 是因为所有的分配请求都来自中断上下文，而所有的进程上下文都在睡眠。对于2.3，
|
| D | zsmalloc.rst | 5 司延腾 Yanteng Si <siyanteng@loongson.cn>
15 是使用单（0-order）页，它将遭受非常高的碎片化 - 任何大小为PAGE_SIZE/2或更大的对象将
18 为了克服这些问题，zsmalloc分配了一堆0-order页面，并使用各种"struct page"字段将它
19 们链接起来。这些链接的页面作为一个单一的higher order页面，即一个对象可以跨越0-order
44 10 192 1 0 2880 2872 135 3
66 组成一个zspage的0-order页面的数量
|
| /Documentation/translations/zh_CN/arch/parisc/ |
| D | debugging.rst | 1 .. include:: ../../disclaimer-zh_CN.rst
7 司延腾 Yanteng Si <siyanteng@loongson.cn>
12 调试PA-RISC
38 3. 有趣的Q位
|
| /Documentation/translations/zh_TW/arch/parisc/ |
| D | debugging.rst | 1 .. include:: ../../disclaimer-zh_TW.rst
7 司延騰 Yanteng Si <siyanteng@loongson.cn>
12 調試PA-RISC
38 3. 有趣的Q位
|
| /Documentation/translations/zh_CN/virt/ |
| D | guest-halt-polling.rst | 1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/virt/guest-halt-polling.rst
7 司延腾 Yanteng Si <siyanteng@loongson.cn>
13 .. _cn_virt_guest-halt-polling:
34 每个vcpu都有一个可调整的guest_halt_poll_ns（"per-cpu guest_halt_poll_ns"），
55 3) guest_halt_poll_grow:
57 当事件发生在per-cpu guest_halt_poll_ns之后但在global guest_halt_poll_ns之前，
58 用于增长per-cpu guest_halt_poll_ns的乘法系数。
86 - 在设置guest_halt_poll_ns参数时应该小心，因为一个大的值有可能使几乎是完全空闲机
|
| D | ne_overview.rst | 1 .. SPDX-License-Identifier: GPL-2.0
2 .. include:: ../disclaimer-zh_CN.rst
8 司延腾 Yanteng Si <siyanteng@loongson.cn>
50 配[2][3]。一个enclave的内存大小需要至少64 MiB。enclave内存和CPU需要来自同
57 enclave通过本地通信通道与主虚拟机进行通信，使用virtio-vsock[5]。主虚拟机有
58 virtio-pci vsock模拟设备，而飞地虚拟机有virtio-mmio vsock模拟设备。vsock
60 virtio-vsock设备获得中断。virtio-mmio设备被放置在典型的4 GiB以下的内存中。
76 连接到主虚拟机的vsock CID和一个预定义的端口--9000，以发送一个心跳值--0xb7。这
83 [1] https://aws.amazon.com/ec2/nitro/nitro-enclaves/
84 [2] https://www.kernel.org/doc/html/latest/admin-guide/mm/hugetlbpage.html
[all …]
|
| /Documentation/translations/zh_CN/scheduler/ |
| D | sched-arch.rst | 1 .. include:: ../disclaimer-zh_CN.rst
3 :Original: Documentation/scheduler/sched-arch.rst
7 司延腾 Yanteng Si <siyanteng@loongson.cn>
40 3. 当cpu_idle发现（need_resched() == 'true'），它应该调用schedule()。否则
59 - 5a. 如果TIF_POLLING_NRFLAG被设置，而我们确实决定进入一个中断睡眠，那
70 sparc - 在这一点上，IRQ是开着的（？），把local_irq_save改为_disable。
71 - 待办事项: 需要第二个CPU来禁用抢占 (参考 #1)
|
123