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/Documentation/ABI/testing/
Dsysfs-devices-edac1 What: /sys/devices/system/edac/mc/mc*/reset_counters
12 What: /sys/devices/system/edac/mc/mc*/seconds_since_reset
19 What: /sys/devices/system/edac/mc/mc*/mc_name
25 What: /sys/devices/system/edac/mc/mc*/size_mb
31 What: /sys/devices/system/edac/mc/mc*/ue_count
39 What: /sys/devices/system/edac/mc/mc*/ue_noinfo_count
46 What: /sys/devices/system/edac/mc/mc*/ce_count
56 What: /sys/devices/system/edac/mc/mc*/ce_noinfo_count
66 What: /sys/devices/system/edac/mc/mc*/sdram_scrub_rate
78 What: /sys/devices/system/edac/mc/mc*/max_location
[all …]
Dsysfs-bus-fsl-mc1 What: /sys/bus/fsl-mc/drivers/.../bind
8 and is the same as found in /sys/bus/fsl-mc/devices/.
12 # echo dpni.2 > /sys/bus/fsl-mc/drivers/fsl_dpaa2_eth/bind
14 What: /sys/bus/fsl-mc/drivers/.../unbind
21 and is the same as found in /sys/bus/fsl-mc/devices/.
25 # echo dpni.2 > /sys/bus/fsl-mc/drivers/fsl_dpaa2_eth/unbind
/Documentation/devicetree/bindings/misc/
Dfsl,qoriq-mc.yaml4 $id: http://devicetree.org/schemas/misc/fsl,qoriq-mc.yaml#
13 The Freescale Management Complex (fsl-mc) is a hardware resource
15 network-oriented packet processing applications. After the fsl-mc
22 For an overview of the DPAA2 architecture and fsl-mc bus see:
54 - fsl,qoriq-mc
56 Must be "fsl,qoriq-mc". A Freescale Management Complex
59 the MC control register region.
68 the second region is the MC control registers. This
75 MC address space and the parent system address space.
77 The MC address space is defined by 3 components:
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/Documentation/ABI/stable/
Dsysfs-bus-fsl-mc1 What: /sys/bus/fsl-mc/rescan
6 force a rescan of fsl-mc bus in the system and
7 synchronize the objects under fsl-mc bus and the
11 What: /sys/bus/fsl-mc/autorescan
17 of the fsl-mc bus is performed. A non-zero value
/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/
Doverview.rst22 A DPAA2 hardware component called the Management Complex (or MC) manages the
23 DPAA2 hardware resources. The MC provides an object-based abstraction for
25 The MC uses DPAA2 hardware resources such as queues, buffer pools, and
28 The MC provides memory-mapped I/O command interfaces (MC portals)
44 +------------------------| mc portal |-+
48 | | Management Complex (MC) | |
61 | -MC portals ... |
67 The MC mediates operations such as create, discover,
70 the MC and are done directly using memory mapped regions in
121 A DPRC has a mappable MMIO region (an MC portal) that can be used
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Dmac-phy-support.rst19 Among other DPAA2 objects, the fsl-mc bus exports DPNI objects (abstracting a
30 Sources of abstracted link state information presented by the MC firmware
42 | | MC firmware
54 | MC firmware polling MAC PCS for link |
62 Depending on an MC firmware configuration setting, each MAC may be in one of two modes:
65 the MC firmware by polling the MAC PCS. Without the need to register a
69 - DPMAC_LINK_TYPE_PHY: The MC firmware is left waiting for link state update
93 dpmac_set_link_state() MC firmware API.
107 (3) In order to configure the HW MAC, the MC Firmware API
132 | MC Firmware |
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Ddpio-driver.rst31 The DPIO driver is bound to DPIO objects discovered on the fsl-mc bus and
41 DPIO object driver-- fsl-mc driver that manages the DPIO object
47 fsl-mc other
84 | MC-bus driver | +------------+
86 | /soc/fsl-mc | |
101 The dpio-driver component registers with the fsl-mc bus to handle objects of
/Documentation/devicetree/bindings/net/
Dfsl,qoriq-mc-dpmac.yaml4 $id: http://devicetree.org/schemas/net/fsl,qoriq-mc-dpmac.yaml#
13 This binding represents the DPAA2 MAC objects found on the fsl-mc bus and
14 located under the 'dpmacs' node for the fsl-mc bus DTS node.
21 const: fsl,qoriq-mc-dpmac
49 compatible = "fsl,qoriq-mc-dpmac";
/Documentation/devicetree/bindings/perf/
Dapm-xgene-pmu.txt9 MC - Memory controller
35 Required properties for MC subnode:
36 - compatible : Shall be "apm,xgene-pmu-mc".
37 - reg : First resource shall be the MC PMU resource.
38 - enable-bit-index : The bit indicates if the according MC is enabled.
90 compatible = "apm,xgene-pmu-mc";
96 compatible = "apm,xgene-pmu-mc";
102 compatible = "apm,xgene-pmu-mc";
108 compatible = "apm,xgene-pmu-mc";
/Documentation/devicetree/bindings/display/tegra/
Dnvidia,tegra186-display.yaml121 #include <dt-bindings/memory/tegra186-mc.h>
159 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
160 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
178 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
179 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
197 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR &emc>,
198 <&mc TEGRA186_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
210 #include <dt-bindings/memory/tegra194-mc.h>
247 interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR &emc>,
248 <&mc TEGRA194_MEMORY_CLIENT_NVDISPLAYR1 &emc>;
[all …]
Dnvidia,tegra20-gr2d.yaml41 - const: mc
64 #include <dt-bindings/memory/tegra20-mc.h>
71 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
72 reset-names = "2d", "mc";
Dnvidia,tegra20-gr3d.yaml87 - const: mc
132 - const: mc
183 - const: mc
205 #include <dt-bindings/memory/tegra20-mc.h>
211 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
212 reset-names = "3d", "mc";
Dnvidia,tegra20-host1x.yaml71 minItems: 1 # MC reset is optional on Tegra186 and later
77 minItems: 1 # MC reset is optional on Tegra186 and later
80 - const: mc
247 #include <dt-bindings/memory/tegra20-mc.h>
257 resets = <&tegra_car 28>, <&mc TEGRA20_MC_RESET_HC>;
258 reset-names = "host1x", "mc";
306 resets = <&tegra_car 21>, <&mc TEGRA20_MC_RESET_2D>;
307 reset-names = "2d", "mc";
314 resets = <&tegra_car 24>, <&mc TEGRA20_MC_RESET_3D>;
315 reset-names = "3d", "mc";
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/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra186-mc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
15 into four 32 bit channels to support LPDDR4 with x16 subpartitions. The MC
32 - nvidia,tegra186-mc
33 - nvidia,tegra194-mc
34 - nvidia,tegra234-mc
46 - description: MC general interrupt
145 const: nvidia,tegra186-mc
164 const: nvidia,tegra194-mc
195 const: nvidia,tegra234-mc
243 compatible = "nvidia,tegra186-mc";
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Dnvidia,tegra20-mc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
27 const: nvidia,tegra20-mc-gart
39 - const: mc
68 compatible = "nvidia,tegra20-mc-gart";
72 clock-names = "mc";
Dnvidia,tegra124-mc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml#
22 const: nvidia,tegra124-mc
32 - const: mc
69 "15.6.1 MC Registers" in the TRM.
117 compatible = "nvidia,tegra124-mc";
120 clock-names = "mc";
Dnvidia,tegra30-mc.yaml4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
39 const: nvidia,tegra30-mc
49 - const: mc
86 "18.13.1 MC Registers" in the TRM.
133 compatible = "nvidia,tegra30-mc";
136 clock-names = "mc";
/Documentation/devicetree/bindings/interconnect/
Dqcom,rpmh.yaml34 - qcom,sc7180-mc-virt
46 - qcom,sc8180x-mc-virt
66 - qcom,sdx55-mc-virt
69 - qcom,sdx65-mc-virt
79 - qcom,sm8150-mc-virt
88 - qcom,sm8250-mc-virt
99 - qcom,sm8350-mc-virt
117 - qcom,sc8180x-mc-virt
119 - qcom,sdx65-mc-virt
/Documentation/devicetree/bindings/devfreq/
Dnvidia,tegra30-actmon.yaml86 #include <dt-bindings/memory/tegra30-mc.h>
88 mc: memory-controller@7000f000 {
89 compatible = "nvidia,tegra30-mc";
92 clock-names = "mc";
107 nvidia,memory-controller = <&mc>;
123 interconnects = <&mc TEGRA30_MC_MPCORER &emc>;
/Documentation/driver-api/
Dedac.rst173 mc/ <existing memory device directory>
209 GPU DF / GPU Node -> EDAC MC
234 $ ls /sys/devices/system/edac/mc/
235 mc0 - CPU MC node 0
249 /sys/devices/system/edac/mc/..
252 ├── mc 0
256 ├── mc 1 # GPU node 0 == mc1, Each MC node has 4 UMCs/CSROWs
279 ├── mc 2 # GPU node 1 == mc2
283 ├── mc 3
285 ├── mc 4
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Dipmb.rst2 IPMB Driver for a Satellite MC
20 Controller or Satellite MC) via IPMB and the device
26 IPMB driver for Satellite MC
29 ipmb-dev-int - This is the driver needed on a Satellite MC to
35 function to set the Satellite MC as an I2C slave.
91 If you have multiple BMCs, each connected to your Satellite MC via
99 Satellite MC
/Documentation/devicetree/bindings/firmware/
Dnvidia,tegra186-bpmp.yaml143 #include <dt-bindings/memory/tegra186-mc.h>
175 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
176 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
177 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
178 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
205 interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
206 <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
207 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
208 <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
/Documentation/devicetree/bindings/edac/
Damazon,al-mc-edac.yaml4 $id: http://devicetree.org/schemas/edac/amazon,al-mc-edac.yaml#
20 const: amazon,al-mc-edac
60 compatible = "amazon,al-mc-edac";
/Documentation/devicetree/bindings/gpu/host1x/
Dnvidia,tegra210-nvdec.yaml88 #include <dt-bindings/memory/tegra186-mc.h>
101 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
102 <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
103 <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
Dnvidia,tegra210-nvjpg.yaml77 #include <dt-bindings/memory/tegra186-mc.h>
90 interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVJPGSRD &emc>,
91 <&mc TEGRA186_MEMORY_CLIENT_NVJPGSWR &emc>;

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