| /Documentation/devicetree/bindings/dma/ |
| D | img-mdc-dma.txt | 1 * IMG Multi-threaded DMA Controller (MDC)
4 - compatible: Must be "img,pistachio-mdc-dma".
5 - reg: Must contain the base address and length of the MDC registers.
10 - sys: MDC system interface clock.
28 mdc: dma-controller@18143000 {
29 compatible = "img,pistachio-mdc-dma";
54 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | cp110-system-controller.txt | 92 …i2sdo_spdifo), ge0(rxd2), tdm(drx), ptp(clk), mss_i2c(sck), uart0(txd), sata1(present_act), ge(mdc)
93 …0(rxd1), tdm(dtx), mss_uart(rxd), ptp(pclk_out), i2c1(sck), uart1(rxd), sata0(present_act), xg(mdc)
95 …, au(i2sbclk), ge0(rxctl), tdm(rstn), mss_uart(rxd), uart1(cts), pcie0(clkreq), uart3(rxd), ge(mdc)
119 …pi1(csn0), mss_gpio5, ge0(rxd2), spi0(csn5), pcie2(clkreq), ptp(pulse), ge(mdc), sata1(present_act…
122 mpp31 31 gpio, dev(a2), mss_gpio4, pcie(rstoutn), ge(mdc)
125 …, sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge(mdc), pcie0(clkreq), ms…
127 …i2c1(sck), ptp(clk), synce1(clk), au(i2sbclk), sata0(present_act), xg(mdc), ge(mdc), pcie2(clkreq)…
128 …(sck), ptp(pclk_out), tdm(intn), mss_i2c(sck), sata1(present_act), ge(mdc), xg(mdc), pcie1(clkreq)…
132 …s_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart1(rxd), ge(mdc), sata1(present_act…
133 …tect), synce2(clk), au(i2smclk), mss_uart(txd), spi0(miso), uart1(cts), xg(mdc), sata0(present_act…
[all …]
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| /Documentation/devicetree/bindings/net/dsa/ |
| D | realtek.yaml | 50 mdc-gpios:
51 description: GPIO line for the MDC clock line.
119 - mdc-gpios
124 mdc-gpios: false
130 - mdc-gpios
137 # - mdc-gpios
152 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
153 mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
246 mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,armada-98dx3236-pinctrl.txt | 18 mpp4 4 gpio, spi0(cs1), smi(mdc), dev(cs0)
45 mpp31 31 gpio, slv_smi(mdc), smi(mdc), dev(we1)
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| D | marvell,armada-39x-pinctrl.txt | 22 mpp4 4 gpio, ua1(txd), ua0(rts), smi(mdc)
25 mpp7 7 gpio, dev(ad9), xsmi(mdc)
38 mpp20 20 gpio, sata0(prsnt) [1], ua0(rts), ua1(txd), smi(mdc)
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| D | marvell,armada-38x-pinctrl.txt | 22 mpp4 4 gpio, ge(mdc), ua1(txd), ua0(rts)
33 mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi)
74 mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
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| D | qcom,ipq4019-pinctrl.yaml | 71 led8, led9, led10, led11, mdc, mdio, pcie, pmu,
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| D | qcom,ipq9574-tlmm.yaml | 72 gcc_plltest, gcc_tlmm, gpio, mac, mdc, mdio, pcie0_clk, pcie0_wake,
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| D | qcom,ipq8074-pinctrl.yaml | 77 mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst,
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| D | qcom,ipq5018-tlmm.yaml | 73 gcc_plltest, gcc_tlmm, gpio, led0, led2, mac0, mac1, mdc, mdio,
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| D | mediatek,mt7622-pinctrl.yaml | 289 I2S3_OUT, I2S4_OUT, GPIO_B, MDC, MDIO, G2_TXD0, G2_TXD1,
394 pins = "MDC";
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| D | marvell,armada-375-pinctrl.txt | 53 mpp37 37 gpio, pcie0(clkreq), tdm(int), ge(mdc)
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| D | marvell,armada-370-pinctrl.txt | 38 mpp17 17 gpo, ge(mdc)
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| /Documentation/devicetree/bindings/spi/ |
| D | spi-img-spfi.txt | 34 dmas = <&mdc 9 0xffffffff 0>, <&mdc 10 0xffffffff 0>;
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| /Documentation/devicetree/bindings/net/ |
| D | fsl,cpm-mdio.yaml | 30 fsl,mdc-pin:
53 fsl,mdc-pin = <13>;
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| D | fsl,fman-mdio.yaml | 33 from which the MDC frequency is derived.
50 become corrupt unless it is read within 16 MDC cycles
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| D | mdio-gpio.yaml | 32 - description: MDC
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| D | qcom,ipq4019-mdio.yaml | 53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
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| D | snps,dwmac.yaml | 514 Frequency division factor for MDC clock.
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| /Documentation/devicetree/bindings/sound/ |
| D | img,spdif-in.txt | 36 dmas = <&mdc 15 0xffffffff 0>;
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| D | img,parallel-out.txt | 36 dmas = <&mdc 16 0xffffffff 0>;
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| D | img,spdif-out.txt | 36 dmas = <&mdc 14 0xffffffff 0>;
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| D | img,i2s-in.txt | 41 dmas = <&mdc 30 0xffffffff 0>;
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| D | img,i2s-out.txt | 42 dmas = <&mdc 23 0xffffffff 0>;
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