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/Documentation/devicetree/bindings/net/
Dbrcm,unimac-mdio.yaml4 $id: http://devicetree.org/schemas/net/brcm,unimac-mdio.yaml#
7 title: Broadcom UniMAC MDIO bus controller
15 - $ref: mdio.yaml#
20 - brcm,genet-mdio-v1
21 - brcm,genet-mdio-v2
22 - brcm,genet-mdio-v3
23 - brcm,genet-mdio-v4
24 - brcm,genet-mdio-v5
25 - brcm,asp-v2.0-mdio
26 - brcm,asp-v2.1-mdio
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Dfsl,fman-mdio.yaml4 $id: http://devicetree.org/schemas/net/fsl,fman-mdio.yaml#
7 title: Freescale Frame Manager MDIO Device
12 description: FMan MDIO Node.
13 The MDIO is a bus to which the PHY devices are connected.
18 - fsl,fman-mdio
20 - fsl,fman-memac-mdio
22 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
23 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
24 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
38 fsl,fman-internal-mdio:
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Dfsl,cpm-mdio.yaml4 $id: http://devicetree.org/schemas/net/fsl,cpm-mdio.yaml#
7 title: Freescale CPM MDIO Device
16 - fsl,pq1-fec-mdio
17 - fsl,cpm2-mdio-bitbang
19 - const: fsl,mpc8272ads-mdio-bitbang
20 - const: fsl,mpc8272-mdio-bitbang
21 - const: fsl,cpm2-mdio-bitbang
26 fsl,mdio-pin:
28 description: pin of port C controlling mdio data
32 description: pin of port C controlling mdio clock
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Dqcom,ipq4019-mdio.yaml4 $id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
7 title: Qualcomm IPQ40xx MDIO Controller
16 - qcom,ipq4019-mdio
17 - qcom,ipq5018-mdio
21 - qcom,ipq6018-mdio
22 - qcom,ipq8074-mdio
23 - qcom,ipq9574-mdio
24 - const: qcom,ipq4019-mdio
36 the first Address and length of the register set for the MDIO controller.
42 - description: MDIO clock source frequency fixed to 100MHZ
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Dhisilicon-hns-mdio.txt1 Hisilicon MDIO bus controller
5 "hisilicon,hns-mdio"
6 "hisilicon,mdio"
7 "hisilicon,hns-mdio" is recommended to be used for hip05 and later SOCs,
8 while "hisilicon,mdio" is optional for backwards compatibility only on
10 - reg: The base address of the MDIO bus controller register bank.
12 - #size-cells: Must be <0>. MDIO addresses have no size component.
14 Typically an MDIO bus might have several children.
17 mdio@803c0000 {
20 compatible = "hisilicon,hns-mdio","hisilicon,mdio";
Dcavium-mdio.txt1 * System Management Interface (SMI) / MDIO
6 "cavium,octeon-3860-mdio": Compatibility with all cn3XXX, cn5XXX
9 "cavium,thunder-8890-mdio": Compatibility with all cn8XXX SOCs.
11 - reg: The base address of the MDIO bus controller register bank.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
17 Typically an MDIO bus might have several children.
20 mdio@1180000001800 {
21 compatible = "cavium,octeon-3860-mdio";
33 * System Management Interface (SMI) / MDIO Nexus
35 Several mdio buses may be gathered as children of a single PCI
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Dmdio-mux-multiplexer.yaml4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
7 title: Properties for an MDIO bus multiplexer consumer device
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
43 mdio-mux-1 { // Mux consumer
44 compatible = "mdio-mux-multiplexer";
46 mdio-parent-bus = <&emdio1>;
50 mdio@0 {
56 mdio@8 {
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Damlogic,gxl-mdio-mux.yaml4 $id: http://devicetree.org/schemas/net/amlogic,gxl-mdio-mux.yaml#
7 title: Amlogic GXL MDIO bus multiplexer
13 This is a special case of a MDIO bus multiplexer. It allows to choose between
14 the internal mdio bus leading to the embedded 10/100 PHY or the external
15 MDIO bus on the Amlogic GXL SoC family.
18 - $ref: mdio-mux.yaml#
22 const: amlogic,gxl-mdio-mux
44 eth_phy_mux: mdio@558 {
45 compatible = "amlogic,gxl-mdio-mux";
51 mdio-parent-bus = <&mdio0>;
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Dallwinner,sun8i-a83t-emac.yaml127 mdio-mux:
133 const: allwinner,sun8i-h3-mdio-mux
135 mdio-parent-bus:
138 Phandle to EMAC MDIO.
146 mdio@1:
147 $ref: mdio.yaml#
149 description: Internal MDIO Bus
153 const: allwinner,sun8i-h3-mdio-internal
178 mdio@2:
179 $ref: mdio.yaml#
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Dapm-xgene-mdio.txt1 APM X-Gene SoC MDIO node
3 MDIO node is defined to describe on-chip MDIO controller.
6 - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi"
12 For the phys on the mdio bus, there must be a node with the following fields:
18 mdio: mdio@17020000 {
19 compatible = "apm,xgene-mdio-rgmii";
27 &mdio {
Dbrcm,mdio-mux-iproc.yaml4 $id: http://devicetree.org/schemas/net/brcm,mdio-mux-iproc.yaml#
7 title: MDIO bus multiplexer found in Broadcom iProc based SoCs.
13 This MDIO bus multiplexer defines buses that could be internal as well as
14 external to SoCs and could accept MDIO transaction compatible to C-22 or
16 properties as well to generate desired MDIO transaction on appropriate bus.
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: brcm,mdio-mux-iproc
30 description: core clock driving the MDIO block
41 mdio_mux_iproc: mdio-mux@66020000 {
42 compatible = "brcm,mdio-mux-iproc";
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Dmdio-mux-mmioreg.yaml4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
19 - $ref: /schemas/net/mdio-mux.yaml#
24 - const: mdio-mux-mmioreg
25 - const: mdio-mux
37 child mdio-mux node must be constrained by this mask.
48 mdio-mux@9 {
49 compatible = "mdio-mux-mmioreg", "mdio-mux";
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Dmdio-gpio.yaml4 $id: http://devicetree.org/schemas/net/mdio-gpio.yaml#
7 title: MDIO on GPIOs
15 - $ref: mdio.yaml#
20 - virtual,mdio-gpio
21 - microchip,mdio-smi0
33 - description: MDIO
36 # Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
44 mdio-gpio0 = &mdio0;
47 mdio0: mdio {
48 compatible = "virtual,mdio-gpio";
Dbrcm,bcm6368-mdio-mux.yaml4 $id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#
7 title: Broadcom BCM6368 MDIO bus multiplexer
13 This MDIO bus multiplexer defines buses that could be internal as well as
15 properties as well to generate desired MDIO transaction on appropriate bus.
18 - $ref: mdio-mux.yaml#
22 const: brcm,bcm6368-mdio-mux
35 mdio0: mdio@10e000b0 {
38 compatible = "brcm,bcm6368-mdio-mux";
41 mdio_int: mdio@0 {
47 mdio_ext: mdio@1 {
Damlogic,g12a-mdio-mux.yaml4 $id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml#
7 title: MDIO bus multiplexer/glue of Amlogic G12a SoC family
10 This is a special case of a MDIO bus multiplexer. It allows to choose between
11 the internal mdio bus leading to the embedded 10/100 PHY or the external
12 MDIO bus.
18 - $ref: mdio-mux.yaml#
22 const: amlogic,g12a-mdio-mux
51 mdio-multiplexer@4c000 {
52 compatible = "amlogic,g12a-mdio-mux";
56 mdio-parent-bus = <&mdio0>;
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Daspeed,ast2600-mdio.yaml4 $id: http://devicetree.org/schemas/net/aspeed,ast2600-mdio.yaml#
7 title: ASPEED AST2600 MDIO Controller
13 The ASPEED AST2600 MDIO controller is the third iteration of ASPEED's MDIO
18 - $ref: mdio.yaml#
22 const: aspeed,ast2600-mdio
26 description: The register range of the MDIO controller instance
42 mdio0: mdio@1e650000 {
43 compatible = "aspeed,ast2600-mdio";
Dmdio-mux.yaml4 $id: http://devicetree.org/schemas/net/mdio-mux.yaml#
7 title: Common MDIO bus multiplexer/switch properties.
13 An MDIO bus multiplexer/switch will have several child busses that are
14 numbered uniquely in a device dependent manner. The nodes for an MDIO
18 mdio-parent-bus:
21 The phandle of the MDIO bus that this multiplexer's master-side port is
31 '^mdio@[0-9a-f]+$':
32 $ref: mdio.yaml#
Dmdio.yaml4 $id: http://devicetree.org/schemas/net/mdio.yaml#
7 title: MDIO Bus Common Properties
15 These are generic properties that can apply to any MDIO bus. Any
16 MDIO bus must have a list of child nodes, one per device on the
22 pattern: '^mdio(-(bus|external))?(@.+|-([0-9]+))?$'
34 lines of all devices on that MDIO bus.
38 RESET pulse width in microseconds. It applies to all MDIO devices
44 Delay after reset deassert in microseconds. It applies to all MDIO
51 Desired MDIO bus clock frequency in Hz. Values greater than IEEE 802.3
75 If set, indicates the MDIO device does not correctly release
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Dti,davinci-mdio.yaml4 $id: http://devicetree.org/schemas/net/ti,davinci-mdio.yaml#
7 title: TI SoC Davinci/Keystone2 MDIO Controller
13 TI SoC Davinci/Keystone2 MDIO Controller
16 - $ref: mdio.yaml#
26 - const: ti,cpsw-mdio
29 - const: ti,am4372-mdio
30 - const: ti,cpsw-mdio
39 description: MDIO Bus frequency
74 davinci_mdio: mdio@4a101000 {
Dfsl-tsec-phy.txt1 * MDIO IO device
3 The MDIO is a bus to which the PHY devices are connected. For each
15 mdio. Currently supported strings/devices are:
17 - "fsl,gianfar-mdio"
19 - "fsl,etsec2-mdio"
20 - "fsl,ucc-mdio"
21 - "fsl,fman-mdio"
22 When device_type is "mdio", the following strings are also considered:
28 mdio@24520 {
30 compatible = "fsl,gianfar-mdio";
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Dallwinner,sun4i-a10-mdio.yaml4 $id: http://devicetree.org/schemas/net/allwinner,sun4i-a10-mdio.yaml#
7 title: Allwinner A10 MDIO Controller
14 - $ref: mdio.yaml#
24 - allwinner,sun4i-a10-mdio
27 - allwinner,sun4i-mdio
40 const: allwinner,sun4i-a10-mdio
56 mdio@1c0b080 {
57 compatible = "allwinner,sun4i-a10-mdio";
Dfsl,enetc-mdio.yaml4 $id: http://devicetree.org/schemas/net/fsl,enetc-mdio.yaml#
7 title: ENETC external MDIO PCIe endpoint device
10 NETC provides an external master MDIO interface (EMDIO) for managing external
12 provides a means for different software modules to share a single set of MDIO
26 - const: fsl,enetc-mdio
36 - $ref: mdio.yaml
47 mdio@0,3 {
48 compatible = "pci1957,ee01", "fsl,enetc-mdio";
Dbrcm,iproc-mdio.yaml4 $id: http://devicetree.org/schemas/net/brcm,iproc-mdio.yaml#
7 title: Broadcom iProc MDIO bus controller
13 - $ref: mdio.yaml#
17 const: brcm,iproc-mdio
29 mdio@18002000 {
30 compatible = "brcm,iproc-mdio";
Dqcom,ipq8064-mdio.yaml4 $id: http://devicetree.org/schemas/net/qcom,ipq8064-mdio.yaml#
7 title: Qualcomm ipq806x MDIO bus controller
13 The ipq806x soc have a MDIO dedicated controller that is
17 - $ref: mdio.yaml#
21 const: qcom,ipq8064-mdio
42 mdio0: mdio@37000000 {
46 compatible = "qcom,ipq8064-mdio";
/Documentation/devicetree/bindings/net/dsa/
Drealtek.yaml18 MDIO or SPI.
21 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
22 not use the MDIO protocol. This binding defines how to specify the
26 The MDIO-connected switches use MDIO protocol to access their registers.
27 The realtek-mdio driver is an MDIO driver and it must be inserted inside
28 an MDIO node.
54 mdio-gpios:
55 description: GPIO line for the MDIO data line.
103 mdio:
104 $ref: /schemas/net/mdio.yaml#
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