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/Documentation/userspace-api/media/dvb/
Dfe-bandwidth-t.rst30 - .. _BANDWIDTH-1-712-MHZ:
34 - 1.712 MHz
38 - .. _BANDWIDTH-5-MHZ:
42 - 5 MHz
46 - .. _BANDWIDTH-6-MHZ:
50 - 6 MHz
54 - .. _BANDWIDTH-7-MHZ:
58 - 7 MHz
62 - .. _BANDWIDTH-8-MHZ:
66 - 8 MHz
[all …]
/Documentation/fb/
Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/Documentation/devicetree/bindings/mfd/
Domap-usb-host.txt40 * "usbhost_120m_fck" - 120MHz Functional clock.
43 * "refclk_60m_int" - 60MHz internal reference clock for UTMI clock mux
44 * "refclk_60m_ext_p1" - 60MHz external ref. clock for Port 1's UTMI clock mux.
45 * "refclk_60m_ext_p2" - 60MHz external ref. clock for Port 2's UTMI clock mux
51 * "usb_host_hs_hsic480m_p1_clk" - Port 1 480MHz HSIC clock gate.
52 * "usb_host_hs_hsic480m_p2_clk" - Port 2 480MHz HSIC clock gate.
53 * "usb_host_hs_hsic480m_p3_clk" - Port 3 480MHz HSIC clock gate.
54 * "usb_host_hs_hsic60m_p1_clk" - Port 1 60MHz HSIC clock gate.
55 * "usb_host_hs_hsic60m_p2_clk" - Port 2 60MHz HSIC clock gate.
56 * "usb_host_hs_hsic60m_p3_clk" - Port 3 60MHz HSIC clock gate.
/Documentation/devicetree/bindings/cpu/
Dcpu-capacity.txt38 by the frequency (in MHz) at which the benchmark has been run, so that
39 DMIPS/MHz are obtained. Such values are then normalized w.r.t. the highest
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
47 representing CPU capacity expressed in normalized DMIPS/MHz. At boot time, the
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
55 mhz values (normalized w.r.t. the highest value found while parsing the DT).
62 The capacities-dmips-mhz or DMIPS/MHz values (scaled to 1024)
128 capacity-dmips-mhz = <1024>;
139 capacity-dmips-mhz = <1024>;
[all …]
/Documentation/devicetree/bindings/clock/
Dsamsung,exynos850-clock.yaml20 two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
73 - description: External reference clock (26 MHz)
89 - description: External reference clock (26 MHz)
107 - description: External reference clock (26 MHz)
125 - description: External reference clock (26 MHz)
143 - description: External reference clock (26 MHz)
167 - description: External reference clock (26 MHz)
187 - description: External reference clock (26 MHz)
207 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
[all …]
Dsamsung,exynosautov9-clock.yaml20 two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
71 - description: External reference clock (26 MHz)
87 - description: External reference clock (26 MHz)
105 - description: External reference clock (26 MHz)
123 - description: External reference clock (26 MHz)
141 - description: External reference clock (26 MHz)
161 - description: External reference clock (26 MHz)
183 - description: External reference clock (26 MHz)
205 - description: External reference clock (26 MHz)
225 - description: External reference clock (26 MHz)
[all …]
Dmaxim,max9485.txt5 - MAX9485_MCLKOUT: A gated, buffered output of the input clock of 27 MHz
15 - clocks: Input clock, must provide 27.000 MHz
34 xo-27mhz: xo-27mhz {
45 clocks = <&xo-27mhz>;
Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
Dtesla,fsd-clock.yaml16 The root clock comes from external OSC clock (24 MHz).
56 - description: External reference clock (24 MHz)
70 - description: External reference clock (24 MHz)
90 - description: External reference clock (24 MHz)
114 - description: External reference clock (24 MHz)
134 - description: External reference clock (24 MHz)
152 - description: External reference clock (24 MHz)
166 - description: External reference clock (24 MHz)
Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
Dsophgo,sg2042-pll.yaml21 - description: Oscillator(Clock Generation IC) for Main/Fixed PLL (25 MHz)
22 - description: Oscillator(Clock Generation IC) for DDR PLL 0 (25 MHz)
23 - description: Oscillator(Clock Generation IC) for DDR PLL 1 (25 MHz)
Dsamsung,exynosautov920-clock.yaml19 two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
66 - description: External reference clock (38.4 MHz)
84 - description: External reference clock (38.4 MHz)
105 - description: External reference clock (38.4 MHz)
123 - description: External reference clock (38.4 MHz)
Dgoogle,gs101-clock.yaml16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
71 - description: External reference clock (24.576 MHz)
87 - description: External reference clock (24.576 MHz)
112 - description: External reference clock (24.576 MHz)
156 - description: External reference clock (24.576 MHz)
/Documentation/devicetree/bindings/net/
Dadi,adin.yaml42 A 25MHz reference and a free-running 125MHz.
44 the 125MHz clocks based on its internal state.
47 - 25mhz-reference
48 - 125mhz-free-running
52 description: Enable 25MHz reference clock output on CLK25_REF pin.
Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
Dqcom,ipq4019-mdio.yaml42 - description: MDIO clock source frequency fixed to 100MHZ
53 MDC rate is feed by an external clock (fixed 100MHz) and is divider
57 To follow 802.3 standard that instruct up to 2.5MHz by default, if
59 default 1.5625Mhz is select.
/Documentation/admin-guide/pm/
Dintel-speed-select.rst154 base-frequency(MHz):2600
168 condition is met, then base frequency of 2600 MHz can be maintained. To
183 base-frequency(MHz):2800
211 This matches the base-frequency (MHz) field value displayed from the
261 Which shows that the base frequency now increased from 2600 MHz at performance
262 level 0 to 2800 MHz at performance level 4. As a result, any workload, which can
263 use fewer CPUs, can see a boost of 200 MHz compared to performance level 0.
424 Specify clos min in MHz with [--min|-n]
425 Specify clos max in MHz with [--max|-m]
434 clos min is not specified, default: 0 MHz
[all …]
/Documentation/devicetree/bindings/media/i2c/
Dsony,imx412.yaml34 description: Clock frequency 6MHz, 12MHz, 18MHz, 24MHz or 27MHz
Dsony,imx415.yaml31 description: Input clock (24 MHz, 27 MHz, 37.125 MHz, 72 MHz or 74.25 MHz)
/Documentation/arch/arm/sunxi/
Dclocks.rst8 Q: Why is the main 24MHz oscillator gateable? Wouldn't that break the
11 A: The 24MHz oscillator allows gating to save power. Indeed, if gated
18 24MHz 32kHz
29 24Mhz 32kHz
/Documentation/scsi/
Ddc395x.rst45 0 20 Mhz
46 1 12.2 Mhz
47 2 10 Mhz
48 3 8 Mhz
49 4 6.7 Mhz
51 6 5 Mhz
52 7 4 Mhz
/Documentation/devicetree/bindings/mips/cavium/
Ductl.txt29 /* 12MHz, 24MHz and 48MHz allowed */
/Documentation/userspace-api/media/drivers/
Dmax2175.rst53 samples/sec with a 10.24 MHz sck.
56 samples/sec with a 32.768 MHz sck.
61 samples/sec with a 14.88375 MHz sck.
64 samples/sec with a 7.441875 MHz sck.
/Documentation/devicetree/bindings/usb/
Drockchip,rk3399-dwc3.yaml27 Controller reference clock, must to be 24 MHz
29 Controller suspend clock, must to be 24 MHz or 32 KHz
31 Master/Core clock, must to be >= 62.5 MHz for SS
32 operation and >= 30MHz for HS operation
Drockchip,dwc3.yaml53 Controller reference clock, must to be 24 MHz
55 Controller suspend clock, must to be 24 MHz or 32 KHz
57 Master/Core clock, must to be >= 62.5 MHz for SS
58 operation and >= 30MHz for HS operation

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