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/Documentation/devicetree/bindings/net/pcs/
Drenesas,rzn1-miic.yaml7 title: Renesas RZ/N1 MII converter
13 This MII converter is present on the Renesas RZ/N1 SoC family. It is
14 responsible to do MII passthrough or convert it to RMII/RGMII.
34 - description: MII reference clock
37 - description: AHB clock used for the MII converter register interface
47 description: MII Switch PORTIN configuration. This value should use one of
56 "^mii-conv@[0-5]$":
58 description: MII converter port
62 description: MII Converter port number.
147 mii_conv1: mii-conv@1 {
[all …]
/Documentation/devicetree/bindings/ptp/
Dtimestamper.txt1 Time stamps from MII bus snooping devices
3 This binding supports non-PHY devices that snoop the MII bus and
6 alone MII time stamping drivers use this binding to specify the
9 Non-PHY MII time stamping drivers typically talk to the control
12 time stamping channels, each of which snoops on a MII bus.
15 stamping channel from the controller device to that phy's MII bus.
40 In this example, time stamps from the MII bus attached to phy@1 will
Dptp-ines.txt6 attributes of PHY nodes. These associate a particular MII bus with a
/Documentation/devicetree/bindings/pinctrl/
Dmarvell,kirkwood-pinctrl.txt33 mii(col)
35 mii(crs)
41 mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
43 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
47 mpp35 35 gpio, mii(rxerr)
71 mii(col), mii-1(rxerr)
73 mii(crs), sata0(prsnt)
79 mpp14 14 gpio, sdio(d0), uart1(rxd), mii(col)
81 mpp16 16 gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
100 mpp35 35 gpio, ge1(rxerr), sata0(act), mii(rxerr)
[all …]
Dmarvell,armada-37xx-pinctrl.txt120 - functions mii, gpio
144 - functions ptp, mii
148 - functions ptp, mii
152 - functions mii, mii_err
190 rgmii_pins: mii-pins {
192 function = "mii";
/Documentation/devicetree/bindings/net/
Dmediatek-dwmac.yaml81 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
83 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
91 For MT2712 RMII/MII interface, Allowed value need to be a multiple of 550,
93 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
112 1. tx clock will be inversed in MII/RGMII case,
122 1. rx clock will be inversed in MII/RGMII case.
Dti,icssg-prueth.yaml48 ti,mii-g-rt:
53 ti,mii-rt:
124 (PRGx_PRU0/1_GPIO10) as input so that the ICSSG MII port is
141 - ti,mii-g-rt
185 ti,pruss-gp-mux-sel = <2>, /* MII mode */
188 <2>, /* MII mode */
204 ti,mii-g-rt = <&icssg2_mii_g_rt>;
Dloongson,ls1c-emac.yaml21 - MII interface
65 - mii
101 phy-mode = "mii";
Dloongson,ls1b-gmac.yaml22 - MII interface
66 - mii
102 phy-mode = "mii";
Dxlnx,axi-ethernet.yaml12 interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
60 - mii
159 phy-mode = "mii";
184 phy-mode = "mii";
Drenesas,ethertsn.yaml14 Gbps full-duplex link via MII/GMII/RMII/RGMII. Depending on the connected PHY.
58 - mii
Dallwinner,sun7i-a20-gmac.yaml63 phy-mode = "mii";
Dsmsc,lan91c111.yaml58 phy-mode = "mii";
Dmscc,miim.yaml7 title: Microsemi MII Management Controller (MIIM)
Dbrcm,bcm7445-switch-v4.0.txt7 - dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt
Drenesas,rzn1-gmac.yaml63 phy-mode = "mii";
Dstm32-dwmac.yaml193 phy-mode = "mii";
208 phy-mode = "mii";
/Documentation/devicetree/bindings/soc/ti/
Dti,pruss.yaml25 - an Ethernet MII_RT module with two MII ports
244 mii-rt@[a-f0-9]+$:
247 MII-RT sub-module represented as a SysCon.
254 - const: ti,pruss-mii
262 mii-g-rt@[a-f0-9]+$:
265 communication protocols (G stands for Gigabit). MII-G-RT sub-module
273 - const: ti,pruss-mii-g
404 pruss_mii_rt: mii-rt@32000 {
405 compatible = "ti,pruss-mii", "syscon";
488 pruss1_mii_rt: mii-rt@32000 {
[all …]
/Documentation/networking/device_drivers/ethernet/davicom/
Ddm9000.rst123 try and read the MII PHY state regularly. This is only available
140 to read the MII state, either when the status changes if we have the
147 expensive MII accesses. This method is faster, but does not print
150 When using an external PHY, the driver currently has to poll the MII
/Documentation/devicetree/bindings/phy/
Dti,phy-gmii-sel.yaml15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
16 The interface mode is selected by configuring the MII mode selection register(s)
26 | |Port 1..<--+-->GMII/MII<------->
41 CPSW Port's Interface Mode Selection PHY describes MII interface mode between
/Documentation/ABI/testing/
Dsysfs-class-net-phydev41 <empty> (not available), mii, gmii, sgmii, tbi, rev-mii,
/Documentation/networking/device_drivers/ethernet/3com/
Dvortex.rst38 - 3c595 Vortex 100base-MII
114 6 MII (Media Independent Interface)
117 9 External MII
306 Donald's mii-diag program may be used for inspecting and manipulating
309 http://www.scyld.com/ethercard_diag.html#mii-diag
389 MII transceiver found at address 24, status 782d.
447 Download mii-diag.c as well. Build these.
449 a) Run 'vortex-diag -aaee' and 'mii-diag -v' when the card is
/Documentation/networking/
Dbonding.rst72 7.3 MII Monitor Operation
506 When this policy is used in conjunction with the mii
575 Specifies the MII link monitoring frequency in milliseconds.
577 inspected for link failures. A value of zero disables MII
791 This delay should be a multiple of the MII link monitor interval
795 to match the value of the MII link monitor interval.
892 Specifies whether or not miimon should use MII or ETHTOOL
894 status. The MII or ETHTOOL ioctls are less efficient and
906 MII / ETHTOOL ioctl method to determine the link state.
909 0 will use the deprecated MII / ETHTOOL ioctls. The default
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/Documentation/devicetree/bindings/net/dsa/
Dlantiq,gswip.yaml30 - const: mii
106 <0xe10b1d8 0x130>; /* mii */
/Documentation/networking/dsa/
Dlan9303.rst6 the two external ethernet ports. The third port is an RMII/MII interface to a

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