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/Documentation/devicetree/bindings/mips/
Dcpus.yaml4 $id: http://devicetree.org/schemas/mips/cpus.yaml#
7 title: MIPS CPUs
32 - mips,m14Kc
33 - mips,mips1004Kc
34 - mips,mips24KEc
35 - mips,mips24Kc
36 - mips,mips4KEc
37 - mips,mips4Kc
38 - mips,mips74Kc
80 compatible = "mips,mips1004Kc";
[all …]
Dmscc.txt1 * Microsemi MIPS CPUs
3 Boards with a SoC of the Microsemi MIPS family shall have the following
Dni.txt1 National Instruments MIPS platforms
/Documentation/devicetree/bindings/bus/
Dmti,mips-cdmm.yaml4 $id: http://devicetree.org/schemas/bus/mti,mips-cdmm.yaml#
7 title: MIPS Common Device Memory Map
10 Defines a location of the MIPS Common Device Memory Map registers.
17 const: mti,mips-cdmm
22 used to map the MIPS CDMM registers block.
34 compatible = "mti,mips-cdmm";
Dpalmbus.yaml13 The ralink palmbus controller can be found in all ralink MIPS
58 #include <dt-bindings/interrupt-controller/mips-gic.h>
Dbaikal,bt1-axi.yaml15 high-speed peripheral IP-cores with RAM controller and with MIPS P5600
84 #include <dt-bindings/interrupt-controller/mips-gic.h>
/Documentation/devicetree/bindings/power/
Dmti,mips-cpc.yaml4 $id: http://devicetree.org/schemas/power/mti,mips-cpc.yaml#
7 title: MIPS Cluster Power Controller
10 Defines a location of the MIPS Cluster Power Controller registers.
17 const: mti,mips-cpc
22 used to map the MIPS CPC registers block.
34 compatible = "mti,mips-cpc";
/Documentation/devicetree/bindings/mips/brcm/
Dsoc.yaml4 $id: http://devicetree.org/schemas/mips/brcm/soc.yaml#
52 mips-hpt-frequency:
53 description: MIPS counter high precision timer frequency.
71 $ref: /schemas/mips/cpus.yaml#
75 - mips-hpt-frequency
105 mips-hpt-frequency = <150000000>;
/Documentation/devicetree/bindings/interrupt-controller/
Dmti,gic.yaml7 title: MIPS Global Interrupt Controller
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
69 MIPS GIC includes a free-running global timer, per-CPU count/compare
107 #include <dt-bindings/interrupt-controller/mips-gic.h>
125 #include <dt-bindings/interrupt-controller/mips-gic.h>
Dmti,cpu-interrupt-controller.yaml7 title: MIPS CPU Interrupt Controller
10 On MIPS the mips_cpu_irq_of_init() helper can be used to initialize the 8 CPU
Dgoogle,goldfish-pic.txt12 Example for mips when used in cascade mode:
/Documentation/translations/zh_TW/arch/mips/
Dfeatures.rst5 :Original: Documentation/arch/mips/features.rst
13 .. kernel-feat:: features mips
Dbooting.rst5 :Original: Documentation/arch/mips/booting.rst
/Documentation/translations/zh_CN/arch/mips/
Dfeatures.rst5 :Original: Documentation/arch/mips/features.rst
13 .. kernel-feat:: features mips
Dbooting.rst5 :Original: Documentation/arch/mips/booting.rst
/Documentation/devicetree/bindings/mips/img/
Dxilfpga.txt7 As we are dealing with a MIPS core instantiated on an FPGA, specifications
41 - compatible: Must be "mips,m14Kc".
43 - clocks: phandle to ext clock for fixed-clock received by MIPS core.
54 compatible = "mips,m14Kc";
/Documentation/devicetree/bindings/mips/ingenic/
Ddevices.yaml4 $id: http://devicetree.org/schemas/mips/ingenic/devices.yaml#
36 - description: MIPS Creator CI20
/Documentation/arch/mips/
Dfeatures.rst3 .. kernel-feat:: features mips
Dindex.rst4 MIPS-specific Documentation
/Documentation/translations/zh_TW/arch/
Dindex.rst11 mips/index
/Documentation/translations/zh_CN/arch/
Dindex.rst11 mips/index
/Documentation/arch/
Dindex.rst17 mips/index
/Documentation/devicetree/bindings/power/reset/
Docelot-reset.txt6 The reset registers are both present in the MSCC vcoreiii MIPS and
/Documentation/devicetree/bindings/clock/
Dbrcm,bcm63xx-clocks.txt1 Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
/Documentation/ABI/testing/
Dsysfs-class-remoteproc3 Contact: Matt Redfearn <matt.redfearn@mips.com>
14 Contact: Matt Redfearn <matt.redfearn@mips.com>

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