Searched full:mmu (Results 1 – 25 of 96) sorted by relevance
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| /Documentation/devicetree/bindings/iommu/ |
| D | samsung,sysmmu.yaml | 7 title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
17 System MMU is an IOMMU and supports identical translation table format to
19 permissions, shareability and security protection. In addition, System MMU has
25 master), but one System MMU can handle transactions from only one peripheral
26 device. The relation between a System MMU and the peripheral device needs to be
31 * MFC has one System MMU on its left and right bus.
32 * FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
34 * M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
35 the other System MMU on the write channel.
37 For information on assigning System MMU controller to its peripheral devices,
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| D | rockchip,iommu.yaml | 33 - description: configuration registers for MMU instance 0
34 - description: configuration registers for MMU instance 1
39 - description: interruption for MMU instance 0
40 - description: interruption for MMU instance 1
59 rockchip,disable-mmu-reset:
62 Do not use the mmu reset operation.
63 Some mmu instances may produce unexpected results
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| D | ti,omap-iommu.txt | 22 back a bus error response on MMU faults.
25 register for enabling the MMU, and the MMU instance
32 /* OMAP3 ISP MMU */
33 mmu_isp: mmu@480bd400 {
43 mmu0_dsp2: mmu@41501000 {
52 mmu1_dsp2: mmu@41502000 {
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| D | arm,smmu.yaml | 7 title: ARM System MMU Architecture Implementation
35 - description: Qcom SoCs implementing "qcom,smmu-500" and "arm,mmu-500"
64 - const: arm,mmu-500
66 - description: Qcom SoCs implementing "arm,mmu-500" (legacy binding)
84 - const: arm,mmu-500
85 - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
105 - const: arm,mmu-500
106 - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
115 - const: arm,mmu-500
131 - description: Marvell SoCs implementing "arm,mmu-500"
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| /Documentation/admin-guide/mm/ |
| D | nommu-mmap.rst | 2 No-MMU memory mapping support
5 The kernel has limited support for memory mapping under no-MMU conditions, such
16 The behaviour is similar between the MMU and no-MMU cases, but not identical;
21 In the MMU case: VM regions backed by arbitrary pages; copy-on-write
24 In the no-MMU case: VM regions backed by arbitrary contiguous runs of
30 shared across fork() or clone() without CLONE_VM in the MMU case. Since
31 the no-MMU case doesn't support these, behaviour is identical to
36 In the MMU case: VM regions backed by pages read from file; changes to
39 In the no-MMU case:
56 are visible in other processes (no MMU protection), but should not
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| /Documentation/virt/kvm/x86/ |
| D | mmu.rst | 4 The x86 kvm shadow mmu
7 The mmu (in arch/x86/kvm, files mmu.[ch] and paging_tmpl.h) is responsible
8 for presenting a standard x86 mmu to the guest, while translating guest
11 The mmu code attempts to satisfy the following requirements:
15 on an emulated mmu except for timing (we attempt to comply
22 minimize the performance penalty imposed by the mmu
62 The mmu supports first-generation mmu hardware, which allows an atomic switch
65 it exposes is the traditional 2/3/4 level x86 mmu, with support for global
72 The primary job of the mmu is to program the processor's mmu to translate
86 number of required translations matches the hardware, the mmu operates in
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| D | index.rst | 14 mmu
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| /Documentation/arch/xtensa/ |
| D | booting.rst | 9 passed to the kernel in the register a2. The address type depends on MMU type:
11 - For configurations without MMU, with region protection or with MPU the
13 - For configurations with region translarion MMU or with MMUv3 and CONFIG_MMU=n
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| D | index.rst | 12 mmu
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| /Documentation/devicetree/bindings/media/ |
| D | img,e5010-jpeg-enc.yaml | 29 - description: The E5010 mmu register region
34 - const: mmu
70 reg-names = "core", "mmu";
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| /Documentation/gpu/amdgpu/ |
| D | amdgpu-glossary.rst | 38 provided an MMU that the GPU could use to get a contiguous view of
39 scattered pages for DMA. The MMU has since moved on to the GPU, but the
49 GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple
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| /Documentation/arch/powerpc/ |
| D | kasan.txt | 17 Currently, only the radix MMU is supported. There have been versions for hash
29 lot of generic device-tree parsing code which is used to determine MMU
39 checks can be delayed until after the MMU is set is up, and we can just not
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| D | booting.rst | 52 The MMU is either on or off; the kernel will run the
76 used by the assembly code to properly disable the MMU
77 in case you are entering the kernel with MMU enabled
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| /Documentation/devicetree/bindings/nios2/ |
| D | nios2.txt | 27 - altr,has-mmu: Specifies CPU support MMU support, should be 1.
61 altr,has-mmu = <1>;
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| /Documentation/driver-api/media/drivers/ |
| D | ipu6.rst | 86 DMA and MMU
90 32-bit virtual address space. The IPU6 has MMU address translation hardware to
94 IPU6 driver. The IPU6 driver sets the level-1 page table base address to MMU
95 register and allows MMU to perform page table lookups.
98 page table entries for each DMA operation and invalidate the MMU TLB after each
112 .. Note:: IPU6 MMU works behind IOMMU so for each IPU6 DMA ops, driver will call
138 memory region via the IPU MMU. The Syscom queues are FIFO fixed depth queues
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| /Documentation/virt/kvm/arm/ |
| D | hyp-abi.rst | 45 Turn HYP/EL2 MMU off, and reset HVBAR/VBAR_EL2 to the initials
57 Mask all exceptions, disable the MMU, clear I+D bits, move the arguments
68 supporting VHE, the EL2 MMU being off, and VHE not being disabled by
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| /Documentation/gpu/ |
| D | drm-vm-bind-locking.rst | 86 userptr gpu_vma on the gpu_vm's userptr list, and in write mode during mmu
94 The write side is held by the core mm while calling mmu interval
102 taken in read mode during exec and write mode during a mmu notifier
397 we are notified using a MMU notifier just before the CPU mm unmaps the
400 When we are notified by the MMU notifier that CPU mm is about to drop the
402 in the MMU notifier and make sure that before the next time the GPU
407 laundry pages, we get such an unmap MMU notification and can mark the
408 pages dirty again before the next GPU access. We also get similar MMU
413 Using a MMU notifier for device DMA (and other methods) is described in
414 :ref:`the pin_user_pages() documentation <mmu-notifier-registration-case>`.
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| /Documentation/devicetree/bindings/gpu/ |
| D | arm,mali-valhall-csf.yaml | 30 - description: MMU interrupt
36 - const: mmu
125 interrupt-names = "job", "mmu", "gpu";
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| D | arm,mali-midgard.yaml | 62 - description: MMU interrupt
68 - const: mmu
161 interrupt-names = "job", "mmu", "gpu";
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| /Documentation/virt/kvm/ |
| D | locking.rst | 26 are taken on the waiting side when modifying memslots, so MMU notifiers
68 the mmu-lock on x86. Currently, the page fault can be fast in one of the
78 What we use to avoid all the races is the Host-writable bit and MMU-writable bit
83 - MMU-writable means the gfn is writable in the guest's mmu and it is not
197 if it can be updated out of mmu-lock [see spte_has_volatile_bits()]; it means
206 As mentioned before, the spte can be updated to writable out of mmu-lock on
211 Since the spte is "volatile" if it can be updated out of mmu-lock, we always
219 when the KVM MMU notifier is called to track accesses to a page (via
271 :Comment: it is a spinlock since it is used in mmu notifier.
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| /Documentation/devicetree/bindings/riscv/ |
| D | cpus.yaml | 65 mmu-type:
67 Identifies the largest MMU address translation mode supported by
175 mmu-type = "riscv,sv39";
198 mmu-type = "riscv,sv48";
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| /Documentation/mm/ |
| D | page_tables.rst | 157 MMU, TLB, and Page Faults
160 The `Memory Management Unit (MMU)` is a hardware component that handles virtual
165 When CPU accesses a memory location, it provides a virtual address to the MMU,
168 MMU uses the page walks to determine the physical address and create the map.
177 There are several reasons why the MMU can't find certain translations. It could
181 When these conditions happen, the MMU triggers page faults, which are types of
225 storage or from other devices, and updates the MMU and its caches.
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| /Documentation/arch/arm/ |
| D | tcm.rst | 30 TCM location and size. Notice that this is not a MMU table: you
37 the MMU, but notice that the TCM is often used in situations where
38 the MMU is turned off. To avoid confusion the current Linux
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| /Documentation/translations/zh_CN/arch/arm64/ |
| D | booting.txt | 164 - 高速缓存、MMU
165 MMU 必须关闭。
207 以上对于 CPU 模式、高速缓存、MMU、架构计时器、一致性、系统寄存器的
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| /Documentation/translations/zh_TW/arch/arm64/ |
| D | booting.txt | 168 - 高速緩存、MMU
169 MMU 必須關閉。
211 以上對於 CPU 模式、高速緩存、MMU、架構計時器、一致性、系統寄存器的
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