| /Documentation/devicetree/bindings/spi/ |
| D | spi-gpio.yaml | 31 mosi-gpios:
32 description: GPIO spec for the MOSI line to use
49 gpio-mosi: false
67 mosi-gpios = <&gpio 97 0>;
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| D | spi-mux.yaml | 16 MOSI /--------------------------------+--------+--------+--------\
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| /Documentation/devicetree/bindings/pinctrl/ |
| D | marvell,kirkwood-pinctrl.txt | 25 mpp1 1 gpo, nand(io3), spi(mosi)
30 mpp6 6 sysrst(out), spi(mosi), ptp(trig)
63 mpp1 1 gpo, nand(io3), spi(mosi)
68 mpp6 6 sysrst(out), spi(mosi), ptp(trig)
107 mpp1 1 gpo, nand(io3), spi(mosi)
112 mpp6 6 sysrst(out), spi(mosi), ptp(trig)
141 mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
156 mpp1 1 gpo, nand(io3), spi(mosi)
161 mpp6 6 sysrst(out), spi(mosi), ptp(trig)
190 mpp27 27 gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
[all …]
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| D | marvell,armada-370-pinctrl.txt | 33 mpp14 14 gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
44 mpp23 23 gpo, ge0(txd7), ge1(txd3), spi1(mosi)
55 mpp34 34 gpo, dev(we0), spi0(mosi)
75 mpp51 51 gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
96 mpp65 65 gpio, spi0(mosi), spi0(cs2)
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| D | marvell,dove-pinctrl.txt | 26 mpp6 6 gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi), pmu*
48 mpp22 22 gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
49 lcd-spi(mosi), uart1(cts), ssp(txd)
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| D | marvell,armada-375-pinctrl.txt | 17 mpp1 1 gpio, dev(ad3), spi0(mosi), spi1(mosi)
47 mpp31 31 gpio, ge1(txd1), spi1(mosi)
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| D | marvell,armada-39x-pinctrl.txt | 33 mpp15 15 gpio, pcie0(rstout), spi0(mosi), i2c1(sck)
41 mpp22 22 gpio, spi0(mosi), dev(ad0)
78 mpp56 56 gpio, ua1(rts), dram(deccerr), spi1(mosi), ua1(txd)
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| D | marvell,armada-38x-pinctrl.txt | 33 mpp15 15 gpio, ge0(rxd3), ge(mdc slave), pcie0(rstout), spi0(mosi)
40 mpp22 22 gpio, spi0(mosi), dev(ad0)
74 mpp56 56 gpio, ua1(rts), ge(mdc), dram(deccerr), spi1(mosi), ua1(txd)
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| D | marvell,armada-xp-pinctrl.txt | 34 mpp13 13 gpio, ge0(txd5), ge1(txd0), spi1(mosi), lcd(d13)
57 mpp36 36 gpio, spi0(mosi)
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| D | marvell,armada-98dx3236-pinctrl.txt | 14 mpp0 0 gpo, spi0(mosi), dev(ad8)
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| D | qcom,msm8960-pinctrl.yaml | 121 mosi-pins {
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| D | mediatek,mt8192-pinctrl.yaml | 172 pins-cs-mosi-clk {
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| /Documentation/devicetree/bindings/arm/marvell/ |
| D | cp110-system-controller.txt | 100 mpp9 9 gpio, dev(ad8), ge0(txd0), spi0(mosi), spi1(mosi), pcie(rstoutn), synce2(clk)
106 mpp15 15 gpio, dev(ad7), spi1(mosi), spi0(mosi), mss_spi(mosi), ptp(pulse_cp2cp)
120 mpp29 29 gpio, dev(csn2), spi1(mosi), mss_gpio6, ge0(rxd1), spi0(csn6), pcie1(clkreq), ptp(clk), ms…
125 mpp34 34 gpio, mii(rxerr), sdio(pwr11), mss_spi(mosi), tdm(dtx), au(i2slrclk), sdio(wr_protect), ge…
132 mpp41 41 gpio, sdio(pwr10), sdio(bus_pwr), mss_i2c(sck), au(i2slrclk), ptp(pulse), spi0(mosi), uart…
139 mpp48 48 gpio, ge1(txctl_txen), spi1(mosi), xg(mdc), wakeup(in_cp2cp)
148 mpp57 57 gpio, mss_i2c(sda), ptp(pclk_out), tdm(intn), au(i2sbclk), spi0(mosi), uart1(txd), sata0(p…
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| D | ap80x-system-controller.txt | 53 mpp2 2 gpio, sdio(d0), spi0(mosi)
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| /Documentation/driver-api/ |
| D | spi.rst | 7 often in the range of 1-20 MHz), a "Master Out, Slave In" (MOSI) data
9 duplex protocol; for each bit shifted out the MOSI line (one per clock)
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| /Documentation/spi/ |
| D | butterfly.rst | 37 MOSI J403.PB2/MOSI pin 9/D7
68 MOSI J403.PE5/DI pin 6/D4
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| D | spi-summary.rst | 15 and parallel data lines with "Master Out, Slave In" (MOSI) or "Master In,
57 Some chips eliminate a signal line by combining MOSI and MISO, and
184 MOSI, and MISO.
506 SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On
635 MOSI XXX__________ _______ _______ ________XXX
654 MOSI idle state configuration
658 MOSI line when the controller is not clocking out data. However, there do exist
659 peripherals that require specific MOSI line state when data is not being clocked
660 out. For example, if the peripheral expects the MOSI line to be high when the
674 MOSI _____ _______ _______ _______________ ___
[all …]
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| /Documentation/devicetree/bindings/leds/ |
| D | leds-spi-byte.txt | 4 - one LED is controlled by a single byte on MOSI
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| /Documentation/devicetree/bindings/leds/irled/ |
| D | ir-spi-led.yaml | 13 IR LED switch is connected to the MOSI line of the SPI device and the data
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| /Documentation/hwmon/ |
| D | lm70.rst | 46 comprise the MOSI/MISO loop. At the end of the transfer, the 11-bit 2's
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| /Documentation/devicetree/bindings/display/panel/ |
| D | samsung,lms397kf04.yaml | 66 mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
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| D | samsung,s6d27a1.yaml | 74 mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
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| D | samsung,lms380kf01.yaml | 73 mosi-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
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| /Documentation/devicetree/bindings/iio/adc/ |
| D | adi,ad7476.yaml | 15 They typically don't provide a MOSI pin, simply reading out data
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| D | adi,ad4000.yaml | 136 # The configuration register can only be accessed if SDI is connected to MOSI
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