| /Documentation/devicetree/bindings/pci/ |
| D | pci-msi.txt | 2 relationship between PCI devices and MSI controllers.
18 Requester ID. A mechanism is required to associate a device with both the MSI
22 For generic MSI bindings, see
23 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
32 - msi-map: Maps a Requester ID to an MSI controller and associated
33 msi-specifier data. The property is an arbitrary number of tuples of
34 (rid-base,msi-controller,msi-base,length), where:
38 * msi-controller is a single phandle to an MSI controller
40 * msi-base is an msi-specifier describing the msi-specifier produced for the
47 the listed msi-controller, with the msi-specifier (r - rid-base + msi-base).
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| D | xgene-pci-msi.txt | 1 * AppliedMicro X-Gene v1 PCIe MSI controller
5 - compatible: should be "apm,xgene1-msi" to identify
6 X-Gene v1 PCIe MSI controller block.
7 - msi-controller: indicates that this is an X-Gene v1 PCIe MSI controller node
9 registers. These registers include the MSI termination address and data
10 registers as well as the MSI interrupt status registers.
16 Each PCIe node needs to have property msi-parent that points to an MSI
23 + MSI node:
24 msi@79000000 {
25 compatible = "apm,xgene1-msi";
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| D | altr,msi-controller.yaml | 5 $id: http://devicetree.org/schemas/altr,msi-controller.yaml#
8 title: Altera PCIe MSI controller
16 - altr,msi-1.0
31 msi-controller: true
44 - msi-controller
48 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
56 msi@ff200000 {
57 compatible = "altr,msi-1.0";
63 msi-controller;
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| D | plda,xpressrich3-axi-common.yaml | 32 - description: builtin MSI controller
38 - const: msi
40 msi-controller:
41 description: Identifies the node as an MSI controller.
43 msi-parent:
44 description: MSI controller the device is capable of using.
68 - msi-controller
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| D | brcm,iproc-pcie.yaml | 63 msi:
65 $ref: /schemas/interrupt-controller/msi-controller.yaml#
71 - const: brcm,iproc-msi
76 brcm,pcie-msi-inten:
80 interrupt enable registers to be set explicitly to enable MSI
82 msi-parent: true
86 brcm,pcie-msi-inten: [msi-controller]
139 msi-parent = <&msi0>;
141 /* iProc event queue based MSI */
142 msi0: msi {
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| D | layerscape-pcie-gen4.txt | 17 none MSI/MSI-X/INTx mode,but there is interrupt line for aer.
19 none MSI/MSI-X/INTx mode,but there is interrupt line for pme.
23 - msi-parent : See the generic MSI binding described in
24 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
44 msi-parent = <&its>;
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 1 This document describes the generic device tree binding for MSI controllers and
9 those busses to the MSI controllers which they are capable of using,
17 they can address. An MSI controller may feature a number of doorbells.
22 MSI controllers may have restrictions on permitted payloads.
28 MSI controller and device rather than a property of either in isolation).
31 MSI controllers:
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
35 address by some master. An MSI controller may feature a number of doorbells.
40 - msi-controller: Identifies the node as an MSI controller.
45 - #msi-cells: The number of cells in an msi-specifier, required if not zero.
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| D | fsl,ls-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,ls-msi.yaml#
7 title: Freescale Layerscape SCFG PCIe MSI controller
15 Each PCIe node needs to have property msi-parent that points to
16 MSI controller node
24 - fsl,ls1012a-msi
25 - fsl,ls1021a-msi
26 - fsl,ls1043a-msi
27 - fsl,ls1043a-v1.1-msi
28 - fsl,ls1046a-msi
33 '#msi-cells':
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| D | loongson,pch-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
7 title: Loongson PCH MSI Controller
14 transforming interrupts from PCIe MSI into HyperTransport vectorized
19 const: loongson,pch-msi-1.0
24 loongson,msi-base-vec:
27 to PCH MSI.
32 loongson,msi-num-vecs:
35 to PCH MSI.
40 msi-controller: true
45 - msi-controller
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| D | msi-controller.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/msi-controller.yaml#
7 title: MSI controller
13 An MSI controller signals interrupts to a CPU when a write is made
14 to an MMIO address by some master. An MSI controller may feature a
18 "#msi-cells":
20 The number of cells in an msi-specifier, required if not zero.
26 The meaning of the msi-specifier is defined by the device tree
27 binding of the specific MSI controller.
30 msi-controller:
32 Identifies the node as an MSI controller.
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| D | fsl,mu-msi.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
25 MU can work as msi interrupt controller to do doorbell
28 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
33 - fsl,imx6sx-mu-msi
34 - fsl,imx7ulp-mu-msi
35 - fsl,imx8ulp-mu-msi
36 - fsl,imx8ulp-mu-msi-s4
67 msi-controller: true
69 "#msi-cells":
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| D | al,alpine-msix.txt | 3 See arm,gic-v3.txt for SPI and MSI definitions.
10 - msi-controller: identifies the node as an PCI Message Signaled Interrupt
12 - al,msi-base-spi: SPI base of the MSI frame
13 - al,msi-num-spis: number of SPIs assigned to the MSI frame, relative to SPI0
22 msi-controller;
23 al,msi-base-spi = <160>;
24 al,msi-num-spis = <160>;
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| D | riscv,imsics.yaml | 7 title: RISC-V Incoming MSI Controller (IMSIC)
14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
32 RISC-V platform. The MSI target address of a IMSIC interrupt file at given
44 - $ref: /schemas/interrupt-controller/msi-controller.yaml#
64 msi-controller: true
66 "#msi-cells":
99 Number of guest index bits in the MSI target address.
105 Number of HART index bits in the MSI target address. When not
113 Number of group index bits in the MSI target address.
122 MSI target address.
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| D | arm,gic-v3.yaml | 115 msi-controller:
182 mbi-ranges: [ msi-controller ]
183 msi-controller: [ mbi-ranges ]
192 # msi-controller is preferred, but allow other names
193 "^(msi-controller|gic-its|interrupt-controller)@[0-9a-f]+$":
197 used to route Message Signalled Interrupts (MSI) to the CPUs.
208 msi-controller: true
210 "#msi-cells":
212 The single msi-cell is the DeviceID of the device which will generate
213 the MSI.
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| D | marvell,odmi-controller.txt | 2 * Marvell ODMI for MSI support
5 which can be used by on-board peripheral for MSI interrupts.
15 - msi-controller : Identifies the node as an MSI controller.
35 msi-controller;
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | msi-pic.txt | 1 * Freescale MSI interrupt controller
5 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
6 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
7 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
8 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
9 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
17 region must be added because different MSI group has different MSIIR1 offset.
21 be set as edge sensitive. If msi-available-ranges is present, only
25 - msi-available-ranges: use <start count> style section to define which
26 msi interrupt can be used in the 256 msi interrupts. This property is
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| /Documentation/PCI/ |
| D | msi-howto.rst | 5 The MSI Driver Guide HOWTO
16 the advantages of using MSI over traditional interrupt mechanisms, how
17 to change your driver to use MSI or MSI-X and some basic diagnostics to
27 The MSI capability was first specified in PCI 2.2 and was later enhanced
28 in PCI 3.0 to allow each interrupt to be masked individually. The MSI-X
30 per device than MSI and allows interrupts to be independently configured.
32 Devices may support both MSI and MSI-X, but only one can be enabled at
73 driver has to set up the device to use MSI or MSI-X. Not all machines
80 To support MSI or MSI-X, the kernel must be built with the CONFIG_PCI_MSI
86 Using MSI
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| /Documentation/PCI/endpoint/ |
| D | pci-test-howto.rst | 79 to change the vendorid and the number of MSI interrupts used by the function
158 SET IRQ TYPE TO MSI: OKAY
191 SET IRQ TYPE TO MSI-X: OKAY
192 MSI-X1: OKAY
193 MSI-X2: OKAY
194 MSI-X3: OKAY
195 MSI-X4: OKAY
196 MSI-X5: OKAY
197 MSI-X6: OKAY
198 MSI-X7: OKAY
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| /Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-flexrm-mbox.txt | 14 - msi-parent: Phandles (and potential Device IDs) to MSI controllers
16 interrupts) to CPU. There is one MSI for each FlexRM ring.
17 Refer devicetree/bindings/interrupt-controller/msi.txt
23 The 2nd cell contains MSI completion threshold. This is the
25 one MSI interrupt to CPU.
27 The 3rd cell contains MSI timer value representing time for
31 specified by this cell then it will inject one MSI interrupt
46 msi-parent = <&gic_its 0x7f00>;
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| /Documentation/devicetree/bindings/misc/ |
| D | fsl,qoriq-mc.yaml | 41 The MSI writes are accompanied by sideband data which is derived from the ICID.
42 The msi-map property is used to associate the devices with both the ITS
45 For generic MSI bindings, see
46 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
102 msi-map:
104 Maps an ICID to a GIC ITS and associated msi-specifier
108 (icid-base,gic-its,msi-base,length).
111 associated with the listed GIC ITS, with the msi-specifier
112 (i - icid-base + msi-base).
114 msi-parent:
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| /Documentation/devicetree/bindings/powerpc/4xx/ |
| D | hsta.txt | 10 Currently only the MSI support is used by Linux using the following
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
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| /Documentation/ABI/testing/ |
| D | sysfs-platform-msi-laptop | 1 What: /sys/devices/platform/msi-laptop-pf/lcd_level
8 What: /sys/devices/platform/msi-laptop-pf/auto_brightness
17 What: /sys/devices/platform/msi-laptop-pf/wlan
24 What: /sys/devices/platform/msi-laptop-pf/bluetooth
33 What: /sys/devices/platform/msi-laptop-pf/touchpad
41 What: /sys/devices/platform/msi-laptop-pf/turbo_mode
54 What: /sys/devices/platform/msi-laptop-pf/eco_mode
64 What: /sys/devices/platform/msi-laptop-pf/turbo_cooldown
75 What: /sys/devices/platform/msi-laptop-pf/auto_fan
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| /Documentation/devicetree/bindings/bus/ |
| D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml#
7 title: Freescale i.MX8qxp Pixel Link Medium Speed Interconnect (MSI) Bus
13 i.MX8qxp pixel link MSI bus is used to control settings of PHYs, I/Os
14 sitting together with the PHYs. It is not the same as the MSI bus coming
18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks,
19 that is, MSI clock and AHB clock, need to be enabled so that peripherals
29 pixel link MSI bus controller and does not allow SCFW user to control it.
43 - fsl,imx8qxp-display-pixel-link-msi-bus
44 - fsl,imx8qm-display-pixel-link-msi-bus
52 - fsl,imx8qxp-display-pixel-link-msi-bus
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| D | xlnx,versal-net-cdx.yaml | 18 and a unique device ID (for MSI) corresponding to a requestor ID
25 The MSI writes are accompanied by sideband data (Device ID).
26 The msi-map property is used to associate the devices with the
43 msi-map: true
62 - msi-map
78 /* define msi map for RIDs 250-259 */
79 msi-map = <250 &its 250 10>;
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| /Documentation/misc-devices/ |
| D | pci-endpoint-test.rst | 17 #) raise MSI IRQ
18 #) raise MSI-X IRQ
36 Tests message signalled interrupts. The MSI number
39 Tests message signalled interrupts. The MSI-X number
43 should be passed as argument (0: Legacy, 1:MSI, 2:MSI-X).
|