Searched full:msis (Results 1 – 14 of 14) sorted by relevance
| /Documentation/PCI/ |
| D | msi-howto.rst | 15 This guide describes the basics of Message Signaled Interrupts (MSIs),
18 try if a device doesn't support MSIs.
21 What are MSIs?
36 Why use MSIs?
39 There are three reasons why using MSIs can give an advantage over
45 a whole. MSIs are never shared, so this problem cannot arise.
54 Using MSIs avoids this problem as the interrupt-generating write cannot
61 MSIs, a device can support more interrupts, allowing each interrupt
69 How to use MSIs
74 support MSIs correctly, and for those machines, the APIs described below
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | msi.txt | 4 Message Signaled Interrupts (MSIs) are a class of interrupts generated by a
7 MSIs were originally specified by PCI (and are used with PCIe), but may also be
12 MSIs are distinguished by some combination of:
57 MSI clients are devices which generate MSIs. For each MSI they wish to
67 This property is unordered, and MSIs may be allocated from any combination of
70 If a device has restrictions on the allocation of MSIs, these restrictions
75 and the set of MSIs they can potentially generate.
112 /* Can only generate MSIs to msi_a */
121 * Can generate MSIs to either A or B.
131 * Can generate MSIs to all of the MSI controllers.
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| D | riscv,imsics.yaml | 14 MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V
20 space to receive MSIs from devices. Each IMSIC interrupt file supports a
21 fixed number of interrupt identities (to distinguish MSIs from devices)
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| D | marvell,sei.txt | 11 MSIs.
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| D | riscv,aplic.yaml | 51 Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
151 // Example 2 (APLIC domains forwarding interrupts as MSIs):
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| /Documentation/devicetree/bindings/pci/ |
| D | apple,pcie.yaml | 26 MSIs are handled by the PCIe controller and translated into regular
27 interrupts. A range of 32 MSIs is provided. These 32 MSIs can be
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| D | pci-msi.txt | 16 MSIs may be distinguished in part through the use of sideband data accompanying
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| /Documentation/arch/powerpc/ |
| D | pci_iov_resource_on_powernv.rst | 24 partitions (i.e., filtering of DMA, MSIs etc.) and to provide a mechanism
33 return all 1's value. MSIs are also blocked. There's a bit more state that
52 For DMA, MSIs and inbound PCIe error messages, we have a table (in
63 - For MSIs, we have two windows in the address space (one at the top of
91 reserved for MSIs but this is not a problem at this point; we just
152 "master PE" which is the one used for DMA, MSIs, etc., and "secondary
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| /Documentation/virt/kvm/devices/ |
| D | mpic.rst | 30 MSIs may be signaled by using this attribute group to write
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| /Documentation/devicetree/bindings/mailbox/ |
| D | brcm,iproc-flexrm-mbox.txt | 15 The FlexRM engine will send MSIs (instead of wired
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| /Documentation/accel/qaic/ |
| D | qaic.rst | 21 non-empty and generate MSIs at a rate equivalent to the speed of the
24 MSIs per second. It has been observed that most systems cannot tolerate this
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| D | aic100.rst | 39 AIC100 implements MSI but does not implement MSI-X. AIC100 prefers 17 MSIs to
41 scenarios where reserving 32 MSIs isn't feasible.
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| /Documentation/devicetree/bindings/powerpc/fsl/ |
| D | msi-pic.txt | 19 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
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| /Documentation/admin-guide/ |
| D | kernel-parameters.txt | 2331 enable MSIs delivered as posted interrupts
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