Searched full:msr (Results 1 – 25 of 50) sorted by relevance
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| /Documentation/trace/ |
| D | events-msr.rst | 2 MSR Trace Events
5 The x86 kernel supports tracing most MSR (Model Specific Register) accesses.
11 /sys/kernel/tracing/events/msr/
13 Trace MSR reads:
17 - msr: MSR number
22 Trace MSR writes:
26 - msr: MSR number
37 cat /sys/kernel/tracing/trace | decode_msr.py /usr/src/linux/include/asm/msr-index.h
39 to add symbolic MSR names.
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| D | index.rst | 22 events-msr
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| /Documentation/virt/kvm/x86/ |
| D | msr.rst | 15 Custom MSR list
18 The current supported Custom MSR list is:
35 guaranteed to update this data at the moment of MSR write.
37 to write more than once to this MSR. Fields have the following meanings:
54 particular MSR is global.
56 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
144 Availability of this MSR must be checked via bit 3 in 0x4000001 cpuid
154 This MSR falls outside the reserved KVM range and may be removed in the
157 Availability of this MSR must be checked via bit 0 in 0x4000001 cpuid
166 This MSR falls outside the reserved KVM range and may be removed in the
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| D | cpuid.rst | 56 writing to msr 0x4b564d02
59 writing to msr 0x4b564d03
63 writing to msr 0x4b564d04
75 when writing to msr 0x4b564d02
83 to msr 0x4b564d05.
91 pf control msr 0x4b564d06 and
92 async pf acknowledgment msr
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| D | index.rst | 15 msr
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| D | errata.rst | 55 MSRs, i.e. {RD,WR}MSR in the guest will behave as expected, but KVM does not
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| /Documentation/arch/powerpc/ |
| D | transactional_memory.rst | 108 delivered. For future compatibility the MSR.TS field should be checked to
112 For 64-bit processes, uc->uc_mcontext.regs->msr is a full 64-bit MSR and its TS
115 For 32-bit processes, the mcontext's MSR register is only 32 bits; the top 32
116 bits are stored in the MSR of the second ucontext, i.e. in
117 uc->uc_link->uc_mcontext.regs->msr. The top word contains the transactional
135 u64 msr = ucp->uc_mcontext.regs->msr;
138 msr |= ((u64)transactional_ucp->uc_mcontext.regs->msr) << 32;
140 if (MSR_TM_ACTIVE(msr)) {
257 kernel via some exception, MSR will end up as TM=0 and TS=01 (ie. TM
259 the MSR and will perform an rfid to do this. In this case rfid can
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| D | ultravisor.rst | 55 * There is a new bit in the MSR that determines whether the current
56 process is running in secure mode, MSR(S) bit 41. MSR(S)=1, process
57 is in secure mode, MSR(s)=0 process is in normal mode.
59 * The MSR(S) bit can only be set by the Ultravisor.
61 * HRFID cannot be used to set the MSR(S) bit. If the hypervisor needs
68 * The privilege of a process is now determined by three MSR bits,
69 MSR(S, HV, PR). In each of the tables below the modes are listed
73 **Secure Mode MSR Settings**
87 **Normal Mode MSR Settings**
993 the MSR value with which to return to the VM.
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| /Documentation/hwmon/ |
| D | fam15h_power.rst | 81 MaxCpuSwPwrAcc MSR C001007b
85 CpuSwPwrAcc MSR C001007a
88 by CU_PTSC MSR C0010280
98 MSR MaxCpuSwPwrAcc.
102 iii. At time x, SW reads CpuSwPwrAcc MSR and samples the PTSC.
106 iv. At time y, SW reads CpuSwPwrAcc MSR and samples the PTSC.
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| /Documentation/arch/x86/ |
| D | sva.rst | 67 A new thread-scoped MSR (IA32_PASID) provides the connection between
69 accesses an SVA-capable device, this MSR is initialized with a newly
86 This MSR is managed with the XSAVE feature set as "supervisor state" to
87 ensure the MSR is updated during context switch.
93 ENQCMD and program it into the new MSR to communicate the process identity to
94 platform hardware. ENQCMD uses the PASID stored in this MSR to tag requests
103 The MSR must be configured on each logical CPU before any application
105 process share the same page tables, thus the same MSR value.
119 IA32_PASID MSR lazily when a thread tries to submit a work descriptor
122 That first access will trigger a #GP fault because the IA32_PASID MSR
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| D | microcode.rst | 125 be in the middle of an access to such an MSR. The usual observation is
126 that such MSR accesses cause #GPs to be raised to signal that former are
168 requests exclusive access to the core before writing to MSR 0x79. So if
205 accessing that MSR will cause a #GP fault.
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| D | pat.rst | 209 configurations. The PAT MSR must be updated by Linux in order to support WC
210 and WT attributes. Otherwise, the PAT MSR has the value programmed in it
211 by the firmware. Note, Xen enables WC attribute in the PAT MSR for guests.
214 MTRR PAT Call Sequence PAT State PAT MSR
237 OS PAT initializes PAT MSR with OS setting
238 BIOS PAT keeps PAT MSR with BIOS setting
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| D | amd-memory-encryption.rst | 56 If support for SME is present, MSR 0xc00100010 (MSR_AMD64_SYSCFG) can be used to
63 If SEV is supported, MSR 0xc0010131 (MSR_AMD64_SEV) can be used to determine if
131 More details in AMD64 APM[1] Vol 2: 15.34.10 SEV_STATUS MSR
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| /Documentation/devicetree/bindings/arm/ |
| D | qcom,coresight-tpdm.yaml | 63 Specifies the number of DSB(Discrete Single Bit) MSR(mux select register)
65 or set to 0, it means this DSB TPDM doesn't support MSR.
72 Specifies the number of CMB MSR(mux select register) registers supported
74 this TPDM doesn't support CMB MSR.
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| /Documentation/trace/postprocess/ |
| D | decode_msr.py | 3 # decode_msr msr-index.h < trace
9 with open(sys.argv[1] if len(sys.argv) > 1 else "msr-index.h", "r") as f:
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| /Documentation/arch/x86/x86_64/ |
| D | fred.rst | 72 base address into the IA32_KERNEL_GS_BASE MSR instead of the GS
78 of the GS base address and that of the IA32_KERNEL_GS_BASE MSR, plus
92 the MSR of the new stack level, i.e., MSR_IA32_FRED_RSP[123].
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| /Documentation/virt/hyperv/ |
| D | clocks.rst | 30 to the guest VM via a synthetic MSR. Hyper-V initialization code
31 in Linux reads this MSR to get the frequency, so it skips TSC
37 The Hyper-V synthetic system clock can be read via a synthetic MSR,
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| /Documentation/admin-guide/hw-vuln/ |
| D | special-register-buffer-data-sampling.rst | 95 IA32_MCU_OPT_CTRL MSR Definition
98 IA32_MCU_OPT_CTRL MSR, (address 0x123). The presence of this MSR and
100 9]==1. This MSR is introduced through the microcode update.
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| D | tsx_async_abort.rst | 15 is 0 in the IA32_ARCH_CAPABILITIES MSR. On processors where the MDS_NO bit
16 (bit 5) is 0 in the IA32_ARCH_CAPABILITIES MSR, the existing MDS mitigations
185 and which get the new IA32_TSX_CTRL MSR through a microcode
186 update. This new MSR allows for the reliable deactivation of
213 provides a TSX control MSR. If so,
225 combinations of CPUID bit MD_CLEAR and IA32_ARCH_CAPABILITIES MSR bits MDS_NO
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| D | processor_mmio_stale_data.rst | 109 is indicated by new bits in MSR IA32_ARCH_CAPABILITIES. As described in a later
116 bits to IA32_ARCH_CAPABILITIES MSR. These bits can be used to enumerate
120 MSR IA32_ARCH_CAPABILITIES
134 Bit 18 - FB_CLEAR_CTRL - Processor supports read and write to MSR
140 MSR IA32_MCU_OPT_CTRL
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| D | multihit.rst | 23 IA32_ARCH_CAPABILITIES MSR.
94 A new bit has been allocated in the IA32_ARCH_CAPABILITIES (PSCHANGE_MC_NO) msr
98 IA32_ARCH_CAPABILITIES MSR Not present Possibly vulnerable,check model
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| /Documentation/virt/kvm/ |
| D | ppc-pv.rst | 124 MSR bits
127 The MSR contains bits that require hypervisor intervention and bits that do
136 If any other bit changes in the MSR, please still use mtmsr(d).
153 mfmsr rX ld rX, magic_page->msr
163 mtmsr rX std rX, magic_page->msr
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| /Documentation/devicetree/bindings/mfd/ |
| D | brcm,bcm59056.txt | 22 csr, iosr1, iosr2, msr, sdsr1, sdsr2, vsr,
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-coresight-devices-tpdm | 166 What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
171 (RW) Set/Get the MSR(mux select register) for the DSB subunit
253 What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]
258 (RW) Set/Get the MSR(mux select register) for the CMB subunit
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| D | sysfs-platform-intel-ifs | 30 the hex value of the STATUS MSR for this test. Note that the error_code field
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