Searched full:msb (Results 1 – 25 of 58) sorted by relevance
123
| /Documentation/sound/soc/ |
| D | dai.rst | 38 MSB is transmitted on the falling edge of the first BCLK after LRC
42 MSB is transmitted on transition of LRC.
45 MSB is transmitted sample size BCLKs before LRC transition.
61 MSB is transmitted on falling edge of first BCLK after FRAME/SYNC.
64 MSB is transmitted on rising edge of FRAME/SYNC.
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| /Documentation/devicetree/bindings/gpio/ |
| D | netxbig-gpio-ext.txt | 6 - addr-gpios: GPIOs representing the address register (LSB -> MSB).
7 - data-gpios: GPIOs representing the data register (LSB -> MSB).
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| /Documentation/hwmon/ |
| D | smsc47b397.rst | 41 HWM Base address can be obtained from Logical Device 8, registers 0x60 (MSB)
73 LSB MSB
83 Reading the tach LSB locks the tach MSB.
89 The tach reading (TCount) is given by: (Tach MSB * 256) + (Tach LSB)
191 OUT DX,AL ; Point to HWM Base Addr MSB
193 IN AL,DX ; Get MSB of HWM Base Addr
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| /Documentation/ABI/testing/ |
| D | sysfs-bus-usb-devices-usbsevseg | 16 MSB 0x06; LSB 0x3F, and
20 MSB 0x08; LSB 0xFF.
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| /Documentation/usb/ |
| D | misc_usbsevseg.rst | 20 MSB 0x06; LSB 0x3f
24 MSB 0x08; LSB 0xff
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| /Documentation/devicetree/bindings/input/ |
| D | gpio-decoder.txt | 6 first entry representing the MSB.
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| /Documentation/input/devices/ |
| D | iforce-protocol.rst | 30 All values are hexadecimal with big-endian encoding (msb on the left). Beware,
65 01 X-Axis msb
67 03 Y-Axis msb, or brake pedal for a wheel
85 04 Address of parameter block changed (msb)
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| /Documentation/devicetree/bindings/hwmon/ |
| D | gpio-fan.yaml | 19 ordered MSB-->LSB.
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| /Documentation/devicetree/bindings/thermal/ |
| D | armada-thermal.txt | 25 "control MSB/control 1", with size of 4 (deprecated binding), or point
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| /Documentation/driver-api/nfc/ |
| D | nfc-pn544.rst | 29 checksum. Firmware update messages have the length in the second (MSB)
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| /Documentation/devicetree/bindings/sound/ |
| D | fsl,sai.yaml | 141 Configures whether the LSB or the MSB is transmitted
143 the MSB is transmitted first as default, or the LSB
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| D | qcom,q6dsp-lpass-ports.yaml | 100 0 = MSB
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| D | audio-graph-port.yaml | 82 - msb
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| /Documentation/devicetree/bindings/bus/ |
| D | brcm,gisb-arb.yaml | 49 appear from MSB to LSB.
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| /Documentation/devicetree/bindings/interrupt-controller/ |
| D | arm,vic.yaml | 46 LSb and ending at source 31 at MSb. A bit that is set means
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| /Documentation/devicetree/bindings/fpga/ |
| D | xlnx,fpga-selectmap.yaml | 16 the clock, with the MSB of each byte presented to the D0 pin.
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| /Documentation/userspace-api/media/v4l/ |
| D | vidioc-g-sliced-vbi-cap.rst | 188 | | msb | lsb | msb | lsb |
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| D | vidioc-enumoutput.rst | 67 The LSB corresponds to audio output 0, the MSB to output 31. Any
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| /Documentation/fb/ |
| D | arkfb.rst | 38 with interleaved planes (1 byte interleave), MSB first. Both modes support
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| D | vt8623fb.rst | 35 with interleaved planes (1 byte interleave), MSB first. Both modes support
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| D | s3fb.rst | 47 with interleaved planes (1 byte interleave), MSB first. Both modes support
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| /Documentation/virt/kvm/x86/ |
| D | timekeeping.rst | 145 set timer to read LSB only and force MSB to zero;
148 0010 - Set Timer 0 MSB mode for port 0x40
149 set timer to read MSB only and force LSB to zero;
153 set timer to read / write LSB first, then MSB;
158 0110 - Set Timer 1 MSB mode for port 0x41 - as described above
163 1010 - Set Timer 2 MSB mode for port 0x42 - as described above
184 01 = MSB only
186 11 = LSB / MSB (16-bit)
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| /Documentation/hid/ |
| D | hid-alps.rst | 78 Byte5 Address - Byte 3 (MSB)
98 Byte5 Address - Byte 3 (MSB)
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| /Documentation/devicetree/bindings/eeprom/ |
| D | at25.yaml | 65 For 9 bits, the MSB of the address is sent as bit 3 of the instruction
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| /Documentation/bpf/ |
| D | classic_vs_extended.rst | 253 (MSB) (LSB)
287 ... and four MSB bits store operation code.
350 (MSB) (LSB)
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