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7 title: Freescale i.MX5 Clock Controller15 for the full list of i.MX5 clock IDs.
14 IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device20 The following RESET_INDEX values are valid for i.MX5:
55 On i.MX5, the internal two-input-multiplexer is used. Due to hardware60 A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
9 The Freescale i.MX5/6 contains an Image Processing Unit (IPU), which71 For more info, refer to the latest versions of the i.MX5/6 reference112 The i.MX5/6 topologies can differ upstream from the IPUv3 CSI video114 is common to all i.MX5/6 platforms. For example, the SabreSD, with the
9 The i.MX7 contrary to the i.MX5/6 family does not contain an Image Processing