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/Documentation/devicetree/bindings/clock/
Dimx5-clock.yaml7 title: Freescale i.MX5 Clock Controller
15 for the full list of i.MX5 clock IDs.
/Documentation/devicetree/bindings/reset/
Dfsl,imx-src.yaml14 IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device
20 The following RESET_INDEX values are valid for i.MX5:
/Documentation/devicetree/bindings/display/imx/
Dldb.txt55 On i.MX5, the internal two-input-multiplexer is used. Due to hardware
60 A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected
/Documentation/admin-guide/media/
Dimx.rst9 The Freescale i.MX5/6 contains an Image Processing Unit (IPU), which
71 For more info, refer to the latest versions of the i.MX5/6 reference
112 The i.MX5/6 topologies can differ upstream from the IPUv3 CSI video
114 is common to all i.MX5/6 platforms. For example, the SabreSD, with the
Dimx7.rst9 The i.MX7 contrary to the i.MX5/6 family does not contain an Image Processing