Searched full:mailbox (Results 1 – 25 of 130) sorted by relevance
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| /Documentation/devicetree/bindings/mailbox/ |
| D | mailbox.txt | 1 * Generic Mailbox Controller and client driver bindings
3 Generic binding to provide a way for Mailbox controller drivers to
4 assign appropriate mailbox channel to client drivers.
6 * Mailbox Controller
9 - #mbox-cells: Must be at least 1. Number of cells in a mailbox
13 mailbox: mailbox {
19 * Mailbox Client
22 - mboxes: List of phandle and mailbox channel specifiers.
25 - mbox-names: List of identifier strings for each mailbox channel.
27 users of these mailboxes for IPC, one for each mailbox. This shared
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| D | ti,omap-mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
7 title: TI OMAP2+ and K3 Mailbox devices
13 The OMAP Mailbox hardware facilitates communication between different
14 processors using a queued mailbox interrupt mechanism. The IP block is
19 Each mailbox IP block/cluster has a certain number of h/w fifo queues and
46 Mailbox Controller Nodes
48 A Mailbox device node is used to represent a Mailbox IP instance/cluster
52 Mailbox Users
55 them using the common mailbox binding properties, "mboxes" and the optional
56 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
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| D | hisilicon,hi6220-mailbox.txt | 1 Hisilicon Hi6220 Mailbox Driver
4 Hisilicon Hi6220 mailbox supports up to 32 channels. Each channel
9 Mailbox Device Node:
15 - reg: Contains the mailbox register address range (base
19 - #mbox-cells: Common mailbox binding property to identify the number
20 of cells required for the mailbox specifier. Must be 3.
22 phandle: Label name of mailbox controller
27 mailbox driver uses it to acknowledge interrupt
28 - interrupts: Contains the interrupt information for the mailbox
34 - hi6220,mbox-tx-noirq: Property of MCU firmware's feature, so mailbox driver
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| D | apple,mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/apple,mailbox.yaml#
7 title: Apple Mailbox Controller
14 The Apple mailbox consists of two FIFOs used to exchange 64+32 bit
16 of this mailbox can be found on Apple SoCs.
31 - apple,t8103-asc-mailbox
32 - apple,t8112-asc-mailbox
33 - apple,t6000-asc-mailbox
34 - const: apple,asc-mailbox-v4
42 - apple,t8103-m3-mailbox
43 - apple,t8112-m3-mailbox
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| D | altera-mailbox.txt | 1 Altera Mailbox Driver
5 - compatible : "altr,mailbox-1.0".
6 - reg : physical base address of the mailbox and length of
8 - #mbox-cells: Common mailbox binding property to identify the number
9 of cells required for the mailbox specifier. Should be 1.
16 mbox_tx: mailbox@100 {
17 compatible = "altr,mailbox-1.0";
24 mbox_rx: mailbox@200 {
25 compatible = "altr,mailbox-1.0";
32 Mailbox client
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| D | microchip,mpfs-mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#
7 title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
14 const: microchip,mpfs-mailbox
19 - description: mailbox control & data registers
20 - description: mailbox interrupt registers
23 - description: mailbox control registers
24 - description: mailbox interrupt registers
25 - description: mailbox data registers
46 mbox: mailbox@37020000 {
47 compatible = "microchip,mpfs-mailbox";
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| D | xgene-slimpro-mailbox.txt | 1 The APM X-Gene SLIMpro mailbox is used to communicate messages between
6 There are total of 8 interrupts in this mailbox. Each used for an individual
7 door bell (or mailbox channel).
12 - reg: Contains the mailbox register address range.
15 the interrupt for mailbox channel 0 and interrupt 1 for
16 mailbox channel 1 and so likewise for the reminder.
18 - #mbox-cells: only one to specify the mailbox channel number.
22 Mailbox Node:
23 mailbox: mailbox@10540000 {
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| D | st,sti-mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/st,sti-mailbox.yaml#
7 title: STMicroelectronics Mailbox Driver for STi platform
10 Each ST Mailbox IP currently consists of 4 instances of 32 channels.
19 const: st,stih407-mailbox
26 description: name of the mailbox IP
29 description: the irq line for the RX mailbox
45 mailbox0: mailbox@8f00000 {
46 compatible = "st,stih407-mailbox";
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| D | xlnx,zynqmp-ipi-mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
7 title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
10 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
41 - xlnx,zynqmp-ipi-mailbox
42 - xlnx,versal-ipi-mailbox
71 Remote Xilinx IPI agent ID of which the mailbox is connected to.
80 '^mailbox@[0-9a-f]+$':
81 description: Internal ipi mailbox node
88 - xlnx,zynqmp-ipi-dest-mailbox
89 - xlnx,versal-ipi-dest-mailbox
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| D | mediatek,gce-props.yaml | 4 $id: http://devicetree.org/schemas/mailbox/mediatek,gce-props.yaml#
15 (CMDQ) mailbox driver is a driver for GCE, implemented using the Linux
16 mailbox framework. It is used to receive messages from mailbox consumers
18 We use mediatek,gce-mailbox.yaml to define the properties for CMDQ mailbox
20 registers is a mailbox consumer. The mailbox consumer can request a mailbox
22 that the GCE thread to configure its hardware. The mailbox provider can also
23 reserve a mailbox channel to configure GCE hardware register by the specific
24 GCE thread. This binding defines the common GCE properties for both mailbox
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| D | marvell,armada-3700-rwtm-mailbox.txt | 1 * rWTM BIU Mailbox driver for Armada 37xx
4 - compatible: must be "marvell,armada-3700-rwtm-mailbox"
5 - reg: physical base address of the mailbox and length of memory mapped
7 - interrupts: the IRQ line for the mailbox
11 rwtm: mailbox@b0000 {
12 compatible = "marvell,armada-3700-rwtm-mailbox";
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| D | rockchip-mailbox.txt | 1 Rockchip mailbox
3 The Rockchip mailbox is used by the Rockchip CPU cores to communicate
6 Refer to ./mailbox.txt for generic information about mailbox device-tree
17 - #mbox-cells: Common mailbox binding property to identify the number
18 of cells required for the mailbox specifier. Should be 1
25 compatible = "rockchip,rk3368-mailbox";
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| D | sprd-mailbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#
7 title: Spreadtrum mailbox controller
17 - sprd,sc9860-mailbox
18 - sprd,sc9863a-mailbox
60 mailbox: mailbox@400a0000 {
61 compatible = "sprd,sc9860-mailbox";
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| D | hisilicon,hi3660-mailbox.txt | 1 Hisilicon Hi3660 Mailbox Controller
3 Hisilicon Hi3660 mailbox controller supports up to 32 channels. Messages
21 - interrupts: : Contains the two IRQ lines for mailbox.
25 mailbox: mailbox@e896b000 {
38 - mboxes : Standard property to specify a Mailbox (See ./mailbox.txt)
50 mboxes = <&mailbox 13 3 0>;
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| D | nvidia,tegra186-hsp.yaml | 4 $id: http://devicetree.org/schemas/mailbox/nvidia,tegra186-hsp.yaml#
26 second cell is used to identify the mailbox that the client is going
32 mailbox to be used (based on the data size). If no flag is
33 specified then, 32-bit shared mailbox is used.
35 Defines the type of the mailbox to be used. This field should be
43 A bit mask of flags that further specify how the shared mailbox
46 Defines the direction of the mailbox. If set, the mailbox
48 cleared, the mailbox is the consumer of data sent by a
52 The index of the shared mailbox to use. The number of available
57 construct mailbox specifiers:
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| D | mtk,adsp-mbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
7 title: Mediatek ADSP mailbox
13 The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
14 to communicate with ADSP by passing messages through two mailbox channels.
15 The MTK ADSP mailbox IPC also provides the ability for one processor to
52 adsp_mailbox0:mailbox@10816000 {
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| D | qcom,cpucp-mbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/qcom,cpucp-mbox.yaml#
7 title: Qualcomm Technologies, Inc. CPUCP Mailbox Controller
13 The CPUSS Control Processor (CPUCP) mailbox controller enables communication
44 mailbox@17430000 {
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| D | allwinner,sun6i-a31-msgbox.yaml | 4 $id: http://devicetree.org/schemas/mailbox/allwinner,sun6i-a31-msgbox.yaml#
14 two-user mailbox controller containing 8 unidirectional FIFOs. An interrupt
20 Refer to ./mailbox.txt for generic information about mailbox device-tree
70 msgbox: mailbox@1c17000 {
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| D | arm,mhuv2.yaml | 4 $id: http://devicetree.org/schemas/mailbox/arm,mhuv2.yaml#
7 title: ARM MHUv2 Mailbox Controller
14 The Arm Message Handling Unit (MHU) Version 2 is a mailbox controller that has
19 Given the unidirectional nature of the controller, an MHUv2 mailbox may only
25 a "receiver" mailbox, otherwise a "sender".
29 as well as the number of provided mailbox channels.
111 mhu: mailbox@2b1f0000 {
117 The above example defines the protocols of an ARM MHUv2 mailbox
169 # Multiple transport protocols implemented by the mailbox controllers
175 mhu_tx: mailbox@2b1f0000 {
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| /Documentation/devicetree/bindings/power/reset/ |
| D | xlnx,zynqmp-power.yaml | 25 Standard property to specify a Mailbox. Each value of
27 mailbox controller device node and an args specifier
28 that will be the phandle to the intended sub-mailbox
30 Documentation/devicetree/bindings/mailbox/mailbox.txt
31 for more details about the generic mailbox controller
33 Documentation/devicetree/bindings/mailbox/ \
34 xlnx,zynqmp-ipi-mailbox.txt for typical controller that
69 // Example with IPI mailbox method:
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| /Documentation/devicetree/bindings/i2c/ |
| D | i2c-xgene-slimpro.txt | 1 APM X-Gene SLIMpro Mailbox I2C Driver
3 An I2C controller accessed over the "SLIMpro" mailbox.
8 - mboxes : use the label reference for the mailbox as the first parameter.
14 mboxes = <&mailbox 0>;
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| /Documentation/ABI/testing/ |
| D | sysfs-driver-intel_sdsi | 13 mailbox. Should the operation fail, one of the following error
19 EIO General mailbox failure. Log may indicate cause.
20 EBUSY Mailbox is owned by another agent.
22 EPROTO Failure in mailbox protocol detected by driver.
27 ETIMEDOUT Failure to complete mailbox transaction in time.
58 a Capability Activation Payload. Mailbox command.
70 fully activate the feature. Mailbox command.
79 utilization metrics of On Demand enabled features. Mailbox
89 information about the current licenses on the CPU. Mailbox
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| /Documentation/devicetree/bindings/serial/ |
| D | nvidia,tegra194-tcu.yaml | 15 systems within the Tegra SoC. It is implemented through a mailbox-
39 List of phandles to mailbox channels used for receiving and
42 - description: mailbox for receiving data from hardware UART
43 - description: mailbox for transmitting data to hardware UART
54 #include <dt-bindings/mailbox/tegra186-hsp.h>
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| /Documentation/devicetree/bindings/hwmon/ |
| D | apm-xgene-hwmon.txt | 3 APM X-Gene SOC sensors are accessed over the "SLIMpro" mailbox.
7 - mboxes : use the label reference for the mailbox as the first parameter.
13 mboxes = <&mailbox 7>;
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| /Documentation/networking/device_drivers/can/freescale/ |
| D | flexcan.rst | 16 - mailbox
23 while the mailbox mode uses a software FIFO with a depth of up to 62
24 CAN frames. With the help of the bigger buffer, the mailbox mode
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
47 This mode activates the "RX mailbox mode" for better performance, on
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